All I/O signals on the AXI EPU IP are synchronized to a
single clock input, aclk
. Read/write access to all control registers using
the s_axi_ctrl interface also uses the same aclk
.
Clock | Description |
---|---|
aclk | Rising edge clock |
All I/O signals on the AXI EPU IP are synchronized to a
single clock input, aclk
. Read/write access to all control registers using
the s_axi_ctrl interface also uses the same aclk
.
Clock | Description |
---|---|
aclk | Rising edge clock |