Address | Name | RW | Default Value | Description |
---|---|---|---|---|
0x10 | ISR | RW | 0x00000000 | Interrupt status and clear. Each bit indicates if
an error condition has occurred. If a Status bit is 1 and the corresponding Mask bit is 0, then the interrupt signal is asserted. Write 1 to a Status bit to clear it. Writes of value 0 have no effect. |
0x14 | IMR | RO | 0x0000003F | Interrupt mask. For each bit:
If an ISR bit is 1 and the corresponding IMR bit is 0, then the interrupt signal is asserted. Read only. Use the IEN and IDS registers to change the mask. |
0x18 | IEN | WO | n/a | Interrupt enable. Write 1 to a bit to enable the corresponding interrupt (set corresponding mask bit to 0). Writes of value 0 have no effect. Reads as zero. |
0x1C | IDS | WO | n/a | Interrupt disable. Write 1 to a bit to disable the corresponding interrupt (set corresponding mask bit to 1). Writes of value 0 have no effect. Reads as zero. |
Fields for each interrupt register are the same:
Field Name | Bits | RW | Notes |
---|---|---|---|
MID_MISS | 0 | Varies | Manager ID miss. The transaction’s SMID, after masking is applied, does not match any manager ID in the manager ID list. |
MID_RO | 1 | Varies | Manager ID read-only violation. The manager attempted a write, but a manager ID list entry matching the request specifies read-only permission. |
SEG_RD_MISS | 2 | Varies | Address segment read miss. A read transaction’s address does not match any address segment in the address segments list, and default read access is not permitted (see CTRL_STATUS: DEF_RD). |
SEG_WR_MISS | 3 | Varies | Address segment write miss. A write transaction’s address does not match any address segment in the address segments list, and default write access is not permitted (see CTRL_STATUS: DEF_WR). |
SEG_MID | 4 | Varies | Address segment manager ID access violation. The transaction manager ID is not permitted to access the address segment containing the transaction address. |
SEG_TZ | 5 | Varies | Address segment TrustZone security violation. A non-secure transaction attempted to access a secure address segment. |