AI Engine Hardware Profile and Debug Methodology - 2023.2 English

AI Engine Tools and Flows User Guide (UG1076)

Document ID: UG1076
Release Date: 2023-12-04
Version: 2023.2 English

Overview
Navigating Content by Design Process
AI Engine Architecture Overview
AI Engine Components
Tools
Documentation
Compiling an AI Engine Graph Application
Setting Up the Vitis Tool Environment
Compile using v++ (Unified Compiler)
v++ Mode AI Engine
AI Engine Options
CDO Options
Compiler Debugging Options
Design Rule Check Options
File Options
Module Specific Options
Event Tracing Options
Optimization Options
Miscellaneous Options
aiecompiler to Unified CLI Migration
Inputs
Outputs
AI Engine Compiler Options
Inline Keywords
Mapper and Router Options
Macro for Device Architectures
Viewing Compilation Results in the Analysis View of the Vitis Unified IDE
Graph and Array Details
Kernels
I/O
Buffers
Ports
Nets
FIFO Depth Evaluation
Tiles
Interface Channels
Compilation Summary
AI Engine Compiler Guidance
Simulating an AI Engine Graph Application
x86 Functional Simulator
Compiling the Design
Simulator Options
Data Snapshots
Deadlock Detection
Trace Report
Memory Access Violations and Valgrind
Using GDB
Macros
Printf() Macros
Using printf() in Kernels
Limitations
Memory Model
Graph API Calls
Preprocessor Considerations
Packet Switching and RTP
Packet Switching
Synchronous and Asynchronous RTP
Best Practices
Software Emulation
Reusing x86 Simulator Options
AI Engine Simulator
Simulator Options
Simulation Input and Output Data Streams
TXT File Format
CSV File Format
Hang Detection
Memory Violations
Simulating Global Memory
Evaluate FIFO Depth To Break Deadlocks
Hardware Emulation
Reusing AI Engine Simulator Options
Enabling Third-Party Simulators
Enabling Third-Party Simulators in a Configuration File
Enabling Third-Party Simulators in the Vitis IDE
External Traffic Generator
Using the Vitis Unified IDE
Migration to Vitis Unified IDE
Migrating Vitis Classic IDE Graph Applications to Vitis Unified IDE
Migrating Command-line Projects to Vitis Unified IDE
Using the Vitis Unified IDE to Build and Simulate AI Engine Components
Creating an AI Engine Component
Defining the AI Engine Config File
Importing Files
Vitis Unified IDE Examples
Building the AI Engine Component
Viewing AI Engine Microcode
Simulating and Debugging the AI Engine Component
Enabling AI Engine Trace
Enabling AI Engine Profile
Enabling AI Engine Pipeline
Debugging an AI Engine Component
Viewing the AI Engine Memory
Viewing AI Engine Registers
Using the Debug Environment
Watchpoints
Variable View and Memory Inspector
Register Inspector
Disassembly View
Multi-Kernel Debug
Viewing Data from Buffer Port Interfaces
Viewing Data from Stream Interfaces
AI Engine Pipeline View
Single Kernel Development
Performance Analysis of AI Engine Graph Application during Simulation
Analyzing AI Engine Status in Hardware Emulation
AI Engine Simulation-Based Performance Analysis
AI Engine Simulation-Based Profiling
AI Engine Simulation-Based Value Change Dump
Generating a VCD File in the IDE
AI Engine Trace from VCD
Generating VCD with Select Signals
Generating a VCD with Select Signals in the IDE
Viewing the Generated VCD in the Vitis Unified IDE
Viewing the Run Summary in the Vitis IDE
Trace View Data Visualization
Window Data Analysis
Supported Window Data Types
Stream Data Analysis
Supported Stream Data Types
Cascade Data Analysis
Scalar RTP Data Analysis
Data Display Limitations
Cross Probing
Trace Compare
AI Engine Stall Analysis in the Vitis IDE
Performance Metrics
Lock Stall Analysis
Stream Stall Analysis
Cascade Stall Analysis
Memory Stall Analysis
FIFO Depth Visualization in the Vitis IDE
DMA FIFO Depth Visualization
Stream Switch FIFO Visualization
Performance Analysis of AI Engine Graph Application on Hardware
Analyzing AI Engine Status in Hardware
Generating AI Engine Status
Analyzing AI Engine Status
Analyzing the Automated Status Output
Analyzing the Manual Status Output
Generating AI Engine Status using XSDB
Profiling the AI Engine
Profiling the AI Engine in Hardware
Profiling the AI Engine, Memory Modules and Interface Tiles
Profiling for AI Engine
Profiling for Memory Modules
Profiling Memory Tiles
Profiling for Interface Tiles
Metric Sets
Profiling Flows
XSDB Flow
XRT Flow
Viewing Profile Results in the Vitis IDE
Event Profile APIs for Graph Inputs and Outputs
Profiling Running Event and Graph Throughput
Profiling Graph Throughput
Profiling Graph Latency
Profiling Graph Bandwidth
Run-Time Event API Performance Counters Usage Summary
Profiling the NoC
Introduction
Procedure to Profile the NMUs Connected to AI Engine
Profile Summary Report Analysis
Limitations
Event Tracing in Hardware
Event Trace Build Flow
Running the Design in Hardware and Capturing Trace Data at Run-Time
XSDB Flow
XRT Flow
Viewing and Analyzing the Trace Data in the Vitis IDE
Using the Delayed Event Trace
Using Multiple Event Trace Streams
Event Trace Offload using High Speed Debug Port
Trace Offload Methodology
Troubleshooting Event Trace in Hardware
Viewing Guidance in the Vitis IDE
Memory Tile Event Trace for AI Engine-ML-based Devices
Programming the PS Host Application
Host Programming on Linux
Controlling the Application with the XRT C++ API
Controlling AI Engine GMIO Transfers
Multi-Process and Multi-Thread Support for Controlling the AI Engine Graph
AI Engine Error Reporting
AI Engine Error Events
Compiling and Linking Host Code for Linux
Compiling and Linking Host Code with ADF API
Host Programming for Bare-Metal
Addressing Kernels in Bare-Metal Applications
Compiling and Linking Host Code for Bare-Metal
Host Programming Support Comparison Between Linux and Bare-Metal
Resetting and Reloading Flow of the AI Engine Array
Generate AI Engine-only and PL-only XCLBIN
Host Application for Reset and Reload Flow
Reset Before Consecutive Application Runs
Mapper/Router Methodology
Design Convergence
Mapping Solution Not Found
Checking User-Defined Constraints
Reducing Window Buffer Sizes for Very High Memory Density Designs
Providing User Guidance to Mapper
Routing Solution Not Found
FIFO Depth Constraints
Area Group Constraints
Relative Constraints
Checking Mapping Results
Event Trace Routing
Improving Design Performance
Memory Stalls
Stream Stalls
Large Skew Between Identical Graph Outputs
AI Engine Hardware Profile and Debug Methodology
Overview of Versal System Profile and Validation Methodology
Hardware Profile and Debug Methodology
Stage 1: Design Execution and System Metrics
Stage 2: System Profiling
Stage 3: PL Kernel Analysis
Stage 4: AI Engine Event Trace and Analysis
Stage 5: Host Application Debug
Summary
Event Trace Reference
Simulation Event Trace
Hardware Event Trace
Encrypting AI Engine Kernels
Mapper/Router Design Rule Checks
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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