Checking Mapping Results - 2021.2 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

Document ID
UG1076
ft:locale
English (United States)
Release Date
2021-12-17
Version
2021.2 English

Check PLIO placement to see if it is causing routing congestion. The most common congestion area for router is in the interface tile region. There are more PLIO channels than there are Interface Channels to connect them into the AI Engine array.

  1. If PLIOs are being constrained make sure adequate resources into the AI Engine array are open to handle the locked PLIOs.
  2. If possible limit PLIO placement near shadow regions to decrease congestion of routing resources.
  3. Check PLIO placement/constraints to verify that crossing such as shown in the following image is not occurring.