In AI Engine simulation and x86 simulation, the PL connections are replaced by files. These files must be provided with already created data for the input and they are created during the simulation runtime for the output. This can be cumbersome when a PL kernel is right in the middle of the graph. In that case, there is no direct relationship between the output values and the re-entered values on the PLIOs.
In software and hardware emulation, you must to provide HLS and/or RTL code for PL located kernels. This can be a problem if these PL kernels are not designed yet.
In order to overcome these difficulties, you can write external traffic generators in Python, C++ or System Verilog. The same traffic generator can be used in simulation and emulation.