The x86 simulator uses a simplified model of the AI Engine architecture. The placement and routing of the various kernels of the AI Engine array is a simplified model in this x86 simulator. The routing delays and FIFO lengths are not modeled in the x86 simulation.
x86 simulations are composed of multiple threads sharing the x86 processor. As a result, memory access conflicts, and stream access conflicts are not modeled.
When targeting the x86 simulator, the AI Engine compiler translates all vector processor specific instructions into a series of x86 instructions. Therefore, the x86 simulator will not estimate any design throughput. Furthermore, software pipelining is not modeled in the x86 simulator.