||This option disables the auto-floor-planning phase in the mapper. This option is useful for heavily constrained designs where you want to guide mapping phase by using location constraints.|
||These options can be used to improve throughput
by reducing memory bank conflicts. At higher BufferOptLevel, mapper
tries to reduce number of buffers getting mapped into same memory
bank, thereby reducing the probability of bank conflicts affecting
overall performance. Higher BufferOptLevels can increase the size of
the overall mapped region, and in few cases, can fail to find a
solution. The default of BufferOptLevels is
||Default trace behavior forces the AI Engine mapper to keep all PLIOs/GMIOs in the original design location when using the trace debug feature. However, if the original solution did not leave any room for trace GMIOs, no solution will be possible unless the design PLIOs are moved. This option is to be used in this case.|
Note: You can recirculate the previous design placement in your next compilation. This significantly reduces the mapper run time. When the compiler runs, it generates a placement constraints file, graph_aie_mapped.aiecst, in the Work/temp directory. Xilinx recommends that you save Work/temp/graph_aie_mapped.aiecst if you want to use it in subsequent compilations because the Work folder is regenerated for every compilation. This constraint file can be specified on the command line for the next iteration.
aiecompiler --constraints Work/temp/graph_aie_mapped.aiecst src/graph.cpp
Tip: The mapper is not aware of the 16K program memory per core limitation. One workaround is to change the run-time usage specification to map kernels to different cores.
||This option ensures DMA FIFOs are only inserted into memory banks that have no other buffers mapped. This option can be used when memory stalls are observed due to DMA FIFO buffers being accessed at the same time as some other design buffer placed in the same bank.|
||Disables the ability of the router to share stream switch FIFOs among two or more terminals of a net. This option should only be used when there are not enough stream switch FIFOs in the device to give each terminal its own individual FIFO(s).|
||Disables the ability for Router to add extra FIFOs onto nets to balance latencies between re-convergent paths.|