PLIO - 2021.2 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

Document ID
UG1076
ft:locale
English (United States)
Release Date
2021-12-17
Version
2021.2 English

This class represents the I/O port attribute specification used to connect AI Engine kernels to the external platform ports representing programmable logic.

Constructor

PLIO(std::string logical_name, std::string datafile);

The above PLIO port attribute specification is used to represent a single 32-bit input or output AXI4-Stream port at the AI Engine array interface as part of a virtual platform specification. The logical_name must be the same as the annotation field of the corresponding port as presented in the logical architecture interface specification. The datafile is an input or output file path that sources input data or receives output data for simulation purposes. This data could be captured separately during platform design and then replayed here for simulation.

PLIO(std::string logical_name, plio_type pliowidth, std::string datafile);

The above PLIO port attribute specification is used to represent a single 32-bit, 64-bit, or 128-bit input or output AXI4-Stream port at the AI Engine array interface as part of a virtual platform specification. Here the pliowidth can be one of plio_32_bits (default), plio_64_bits, or plio_128_bits.

PLIO(std::string logical_name, plio_type pliowidth, std::string datafile, double frequency);

The above PLIO port attribute specification is used to represent a single 32-bit, 64-bit, or 128-bit input or output AXI4-Stream port at the AI Engine array interface as part of a virtual platform specification. Here pliowidth can be one of plio_32_bits (default), plio_64_bits, or plio_128_bits. The frequency of the PLIO port can also be specified as part of the constructor.

PLIO(std::string logical_name, plio_type pliowidth, std::string datafile, double frequency, bool binary, bool hex);

The above PLIO boolean port attribute specification is used to indicate if the contents in the input data file are in hex or binary formats.

The data in the data files must be organized according to the bus width of the PLIO attribute (32, 64, or 128) per line as well as the data type of the graph port it is connected to. For example, a 64-bit PLIO feeding a kernel port with data type int32 requires file data organized as two columns. However, the same 64-bit PLIO feeding to a kernel port with data type cint16 requires the data to be organized into four columns, each representing a 16-bit real or imaginary part of the complex data type.