A platform is a fully contained image that defines both the hardware (XSA) as well as the software (bare metal, Linux, or both). The XSA contains the hardware description of the platform, which is defined in the Vivado Design Suite, and the software is defined with the use of a bare-metal setup, or a Linux image defined through PetaLinux.
Types of Platforms
- Base platform: A base platform is one that is provided by
Xilinx (for example, the
xilinx_vck190_base_202220_1) typically targeting Xilinx boards. If a platform is called a base platform, it is a static platform. For static platforms, the hardware link result contains the full bit configuration. During system boot, this full bit is loaded. When the host application executes the XCLBIN file, it only reads the metadata from XCLBIN.
- DFX platform: A DFX platform can dynamically load a Kernel
PL configuration during run time. When the system boots, only platform
hardware is loaded. When the host application downloads the XCLBIN file, it
runs partial reconfiguration for the DFX region and reads the metadata from
XCLBIN. For example, the
xilinx_vck190_base_dfx_202220_1platform contains one DFX region that includes both AI Engine and PL Kernels.
- Custom platform: A custom platform is one that you can create, either by extending or re-customizing a base or base DFX platform, or creating a new platform. When starting platform development, it can be useful to use a base platform or base DFX platform from Xilinx as a reference development platform to create your custom platform.
This chapter takes the base platform, for example,
xilinx_vck190_base_202220_1, to show command usage. For targeting the
Targeting the DFX Platform.
You can create platforms by customizing an existing base platform (for example, changing the AI Engine clock frequency, clocks available in the programmable logic (PL), changing memory controller settings) or create a new platform targeting Xilinx or non-Xilinx boards. Creating a platform allows you to provide your own IP or subsystems to meet your needs. The process to create a platform can be found in Creating Embedded Platforms in Vitis in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).
Platforms have a variety of clocking: processor, PL, and AI Engine clocking. The following table explains the clocking for each.
|AI Engine||Can be configured in the platform in the AI Engine IP.|
|Processor||Can be configured in the platform in the CIPS IP.|
|Programmable Logic (PL)||Can have multiple clocks and can be configured in the platform.|
|NoC||Device dependent and can be configured in the platform in the CIPS and NoC IP.|
For more information related to platform clocking, see Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393). For information on Versal device clocks, see Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957).