Platforms - 2021.2 English

Versal ACAP AI Engine Programming Environment User Guide (UG1076)

Document ID
UG1076
ft:locale
English (United States)
Release Date
2021-12-17
Version
2021.2 English

A platform is a fully contained image that defines both the hardware (XSA) as well as the software (bare metal, Linux, or both). The XSA contains the hardware description of the platform, which is defined in the Vivado Design Suite, and the software is defined with the use of a bare-metal setup, or a Linux image defined through PetaLinux.

Types of Platforms

There are two types of platforms: base platform, or custom platform. A base platform is one that is provided by Xilinx (for example, the xilinx_vck190_base_202120_1) typically targeting Xilinx boards, and a custom platform is one that you can create, either by extending or re-customizing a base platform or creating a new platform. When starting platform development, it can be useful to use a base platform as a reference development platform to create your custom platform.

Custom Platforms

You can create platforms that can re-customize an existing base platform (for example, changing the AI Engine clock frequency, clocks available in the programmable logic (PL), changing memory controller settings) or create a new platform targeting Xilinx or non-Xilinx boards. Creating a platform allows you to provide your own IP or subsystems to meet your needs. The process to create a platform can be found in Creating Embedded Platforms in Vitis in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).

Platform Clocking

Platforms have a variety of clocking: processor, PL, and AI Engine clocking. The following table explains the clocking for each.

Table 1. Platform Clocks
Clock Description
AI Engine Can be configured in the platform in the AI Engine IP.
Processor Can be configured in the platform in the CIPS IP.
Programmable Logic (PL) Can have multiple clocks and can be configured in the platform.
NoC Device dependent and can be configured in the platform in the CIPS and NoC IP.
  1. These clocks are derived from the platform and are affected by the device, speed grade and operating voltage.

For more information related to platform clocking, see Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393). For information on Versal device clocks, see Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957).