This chapter describes the various execution targets available to simulate AI Engine applications at different levels of abstraction, accuracy, and speed. AI Engine graphs can be simulated in four different simulation environments.
The x86 simulator is a fast-functional simulator as described in x86 Functional Simulator. It should be used to functionally simulate your AI Engine graph and is useful for functional development and verification of kernels and graphs. It, however, does not provide timing, resource, or performance information.
The AI Engine simulator
aiesimulator) models the timing and resources of the AI Engine array, while using transaction-level SystemC
models for the NoC, DDR memory. This allows for faster performance analysis of your
AI Engine applications and accurate estimation of
the AI Engine resource use, with cycle-approximate
In both x86 functional simulator and AI Engine simulator, PL interface to AI Engine can be exercised through untimed external traffic. Similarly, both use the user graph’s main() function as C-test bench to configure and control the AI Engine. This test bench data input and output is not timed, and the user graph’s main() function acts as a virtual simulation platform.
When you want a fast functional simulation of the entire system including the AI Engine graph, the PL logic along with XRT-based host application to control the AI Engine and PL, you should use the Vitis™ software emulation flow. The software emulation flow enables using HLS-based kernels or C-models of RTL based kernels to be interfaced with AI Engine graph and controlled using host code which can also be run on hardware. This flow includes the x86 functional model of the AI Engine and the PS. The x86 functional model of the PS is the default model in the software emulation flow. The Arm QEMU model is available as an alternative model for the PS as well.
Finally, when you are ready to simulate the entire system including AI Engine graph and PL logic along with XRT-based host application to control the AI Engine and PL, for a specific board and platform, you should use the Vitis hardware emulation flow. This flow includes the SystemC model of the AI Engine, transaction-level SystemC models for the NoC, DDR memory, PL Kernels (RTL), and PS (running on QEMU). You can also include RTL logic and test bench PL logic for your platform or design.
The following table lists the four simulation flows and whether they support functional or performance level debug, and the level of support for source code debug. It also recommends the usage of these simulation flows in appropriate stages of your AI Engine design development.
|Simulation Tool Flow||Functional Debug||Performance Analysis and Debug||Source Level Debug||Design Development Stage Usage|
|x86 Simulator||Yes||No||Yes||AI Engine kernel and graph debug|
|AI Engine Simulator||Yes||Yes (This simulation steps through the AI Engine assembly code and is useful in performance analysis, as well as optimization)||Allows stepping through the AI Engine compiler generated assembly code which aids in code optimization, however, source level visibility could be limited due to compiler optimization||AI Engine graph performance debug|
|Vitis Software Emulation||Yes||No||Yes||System level emulation and functional debug|
|Vitis Hardware Emulation||Yes||Yes||Possible—however, provides limited source level visibility due to compiler optimization||System level emulation and performance debug|
The following table lists the simulation flows and recommends the usage of these simulation flows in appropriate stages of your AI Engine design development and the type of simulation model used for the various Versal® architecture domains. The type of simulation model and the simulation tool flow used determine the accuracy of the simulation results.
|Simulation Tool Flow||AI Engine Kernels||PL Kernels||PL Platform||NoC/DDR Model||PS Model|
|x86 Simulator||x86 threads||C/SystemC/External traffic generators||N/A||N/A||N/A|
|AI Engine Simulator||SystemC||SystemC/External traffic generators||N/A||SystemC||N/A|
|Vitis Software Emulation||x86 threads||SystemC/RTL/External traffic generators||N/A||N/A||x86 (default) QEMU (optional)|
|Vitis Hardware Emulation||SystemC||SystemC/RTL/External traffic generators||RTL/SystemC||SystemC||QEMU|
You can obtain profiling data when you run your design in
aiesimulator or hardware emulation. Analyzing this
data helps you gauge the efficiency of the kernels, the stall and active times
associated with each AI Engine, and pinpoint the
AI Engine kernel whose performance might not
be optimal. This also allows you to collect data on design latency, throughput, and
bandwidth. Details on running and analyzing profile data can be found in Performance Analysis of AI Engine Graph Application during Simulation.
The event trace feature allows you to capture and analyze a system-level view of program execution. It can be helpful in identifying problems during program execution including correctness and performance issues. The AI Engine architecture has direct support for generation, collection, and streaming of events as trace data during simulation and hardware emulation. Details on running and analyzing event trace data can be found in Performance Analysis of AI Engine Graph Application during Simulation.
aiesimulator simulate the design via the
main() function of
graph.cpp. QEMU emulation support is available for host applications
in software emulation and hardware emulation. Note that QEMU support is optional in
software emulation. In software emulation, you can create a host application
targeting Linux-XRT and emulate the host application. In hardware emulation, you can
create a host application targeting Baremetal or Linux-XRT and emulate the host
application as well. Test bench data can be provided to the x86 simulator and
AI Engine simulator via the graph’s main()
function which acts like a virtual test bench platform. There are various levels of
test bench support available for the simulation flows. Test bench data can either be
file based or via an external traffic generator. Additional details on this feature
can be found in Generating Traffic for Simulation and Emulation.
The data flowing between the AI Engine kernels is available and can be viewed either as data snapshot files or via the Vitis Analyzer GUI. Additional details on the x86 simulator snapshot feature can be found in Data Snapshots. Additional information on data visualization of trace data on the results of running the AI Engine simulator can be found in Trace View Data Visualization.
The following table lists the type of simulation features supported with the four simulation flows.
|Simulation Tool Flow||Trace||Profile||Host Application||Test Bench Support||AI Engine Data Flow Visibility|
|x86 Simulator||No||No||Through the main() function in graph.cpp||File-based/External traffic generators||Yes (via the snapshot feature)|
|AI Engine Simulator||Yes||Yes||Through the main() function in graph.cpp||File-based/External traffic generators||Yes (via Trace view in Vitis Analyzer)|
|Vitis Software Emulation||No||No||Through the main() function in host application targeting Linux-XRT||File-based/External traffic generators||Yes (via the snapshot feature)|
|Vitis Hardware Emulation||Yes||Yes||Through the main() function in host application targeting BareMetal or Linux-XRT||File-based/External traffic generators||Yes (via Trace view in Vitis Analyzer)|