FIFO Location Constraints - 2023.2 English

The aiecompiler tries to automatically allocate FIFOs in the most efficient manner possible. However, you might want to explicitly control their placement in memory, as shown in the following example. This constraint is useful to preserve the placement of FIFO resources between runs of the aiecompiler.

Note the following considerations for FIFO constraints.

• If FIFO constraints are used, the entire depth of the FIFO must be constrained. It is not possible to constrain a portion of the FIFO and leave the rest for the compiler to add.
• If FIFO constraints are added to branching nets, the FIFO constraint should be added to each point-to-point net. If you want to share stream switch FIFOs or DMA FIFOsbefore the branch, this can be achieved by duplicating the FIFO type and location on each point-to-point net.
• The constraint can be used without a location to specify the desired type of FIFO without specifying a location or depth.

The following example shows how a FIFO constraint can be used in a graph file.

two_node_graph() {
  loop0 = kernel::create(loopback_stream);
  loop1 = kernel::create(loopback_stream);
  loop2 = kernel::create(loopback_stream);

  source(loop0) = "loopback_stream.cc";
  source(loop1) = "loopback_stream.cc";
  source(loop2) = "loopback_stream.cc";

  connect net0 (in0, loop0.in[0]);
  connect net1 (loop0.out[0], loop1.in[0]);
  connect net2 (loop1.out[0], loop2.in[0]);
  connect net3 (loop2.out[0], out0);

  runtime(loop0) = 0.9;
  runtime(loop1) = 0.9;
  runtime(loop2) = 0.9;

  fifo_depth(net1) = 32;
  fifo_depth(net2) = 48;

  location< fifo >(net1) = {ss_fifo(shim_tile, 16 , 0, 1), ss_fifo(shim_tile,17,0,0)};
  location< fifo >(net2) = dma_fifo(aie_tile, 8, 0, 0x0000, 48);
};

The second example shows how a FIFO constraint can be added to a constraints file.

{
  "PortConstraints": {
    "fifo_locations_records": {
      "dma_fifos": {
        "r1": {
          "tile_type": "core",
          "row": 0,
          "column": 0,
          "size": 16,
          "offset": 8,
          "bankId": 2
        },
        "r2": {
          "tile_type": "core",
          "row": 0,
          "column": 1,
          "size": 16,
          "offset": 9
        },
        "r4": {
          "tile_type": "mem",
          "row": 2,
          "column": 4,
          "size": 16,
          "offset": 6,
          "bankId": 2
        }
      },
      "stream_fifos": {
        "r3": {
          "tile_type": "shim",
          "row": 1,
          "column": 3,
          "channel": 1
        }
      }
    },
    "mygraph.k2.in[0]": {
      "fifo_locations": ["r1", "r2", "r3"]
    },
    "mygraph.k4.in[0]": {
      "fifo_locations": ["r1", "r2", "r4"]
    }
  }
}