Vitis Unified IDE manages the AI Engine components and system project. The Vitis Unified IDE provides views for AI Engine kernel development, and it is essential in the kernel development, debugging, and analysis.
Vitis Unified IDE has a debug view which displays registers, variables, available breakpoints, variables to register/memory mapping, internal/external memory contents, Disassembly view, and Pipeline view for instructions.
When launching the simulation, if Enable Profile is selected in launch
configurations, it will show the
printf output in
console. The Enable Trace
check box in launch configurations is for generating event trace data which helps
better understand when and how events such as memory stall and stream stall have
occurred. Event trace is helpful in performance tuning.
When launching the debug perspective, if Enable Pipeline View is selected in launch configurations, the AI ENGINE PIPELINE view can be shown.
In the debug perspective, debug commands enable you to resume, step into, and step over. The AI Engine source code is shown, and it is possible to set breakpoints by double-clicking lines. The windows Variables, Breakpoints, and Register Inspector are available to look into data memory or register status. The Disassembly view is helpful in understanding how instructions are used, especially how they are scheduled in the pipeline. The Pipeline view allows you to correlate instructions executed in a specific clock cycle with the labels in the Disassembly view.
The generated code for an AI Engine (
Col_Row.cc) includes the AI Engine kernels in the core and wrapper code. From
the AI Engine wrapper code, you can step into the
AI Engine kernel code by clicking multiple
step-in buttons. Alternatively, you can open the AI Engine kernel source file from the design perspective, and set
breakpoints in the file. Multiple views, such as the Disassembly view,
Register Inspector, and
Variables view can be used for debug,
and performance tuning.
The Disassembly view displays the compiler generated instruction target to the hardware. C/C++ source code can also be embedded between the lines for source code referencing. The instruction helps understand the compiled result, especially the loop pipelining result. By scrolling or stepping in the Disassembly view, the loop in the kernel can be found. The loop iterates from zero-overhead loop start (ZLS) to zero-overhead loop end (ZLE). It can be seen how load instructions and MAC instructions are placed to be pipelined. The preamble and postamble instructions are placed before and after the zero-overhead loop body to fill and flush the pipeline stages.
The Microcode view provides a static view of compiled kernel instructions. It can be opened via AI Engine components or links in Tile view in the analysis view in the Vitis IDE. By right-click the Microcode view, set the option to Enable AIE Cross Probing. Cross probing occurs between the Microcode view and source code.