The legacy Quad-SPI controller supports the following 3-byte address commands. The number of data lanes (DQ pins) for sending the instruction, opcode, and data and receiving the data listed in Table: 4-byte Address Support. The legacy Quad-SPI controller does not support instructions where the flash device requires using a different number of data lanes for the same instruction code.
Table 24-8: 3-Byte Address Support
Command Number
|
Instruction Code
|
Address Bytes
|
Data Lanes Used for Opcode
|
Data Lanes Used for Address
|
Data Lanes Used for Data
|
Command Type
|
1
|
8'h05
|
3 bytes
|
1
|
–
|
1
|
Read status register
|
2
|
8'h03
|
3 bytes
|
1
|
1
|
1
|
Read normal
|
3
|
8'h0B
|
3 bytes
|
1
|
1
|
1
|
Read fast
|
4
|
8'h3B
|
3 bytes
|
1
|
1
|
2
|
Read dual output
|
5
|
8'h6B
|
3 bytes
|
1
|
1
|
4
|
Read quad output
|
6
|
8'hBB
|
3 bytes
|
1
|
2
|
2
|
Read dual I/O
|
7
|
8'hEB
|
3 bytes
|
1
|
4
|
4
|
Read quad I/O
|