64-bit ECC Support

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The OCM supports 64-bit wide ECC functionality to detect multi-bit errors and recover from a single-bit memory fault. The syndrome bits are calculated on a 64-bit basis. For every 64 bits processed by the ECC, both write channels generate and append eight additional syndrome bits. This adds 32 syndrome bits per memory location (256 bit).

On a write, if all bytes are being written, the ECC is generated (on a per 64-bit basis) and written into the ECC RAM along with the write-data that is written into the data RAM. If one or more bytes are not written (the byte enables are disabled), then the data RAM is first read, and the read data is corrected and merged with the write data. The merged write data is written with all bytes enabled. If the read (of the read-modify-write operation) results in an uncorrectable error, then the write is not performed and an AXI SLVERR is generated.

If a correctable or uncorrectable error is detected during a read, then the read address is captured in the ocm.OCM_{CE, UE}_FFA registers, depending on the type of error. For a correctable error, an optional interrupt is generated. If the ECC error status register (OCM_ISR) is not cleared by software, any further error information is not recorded.

1-bit or 2-bit errors per 64-bit (ECC WORD) can be injected based on the memory-mapped register value (64 + 8 bits) that is XOR-ed with the written data and syndrome.