The ACE is backwards compatible to AXI4 and supports coherent interconnects. In addition to five AXI4 channels, ACE adds three additional snoop channels and some extra signals. The ACADDR channel is a snoop-address input to the master. The CRRESP channel is used by the master to signal the response to snoops to the interconnect. The CDDATA channel is output from the master to transfer snoop data to the originating master and/or external memory. ARSNOOP and AWSNOOP indicate the type of snoop transactions for shareable transactions on the read and write channels, respectively. ARBAR and AWBAR are used for barrier signaling. ARDOMAIN indicates the masters to snoop for snoop transactions and the masters to be considered or the ordering of barrier transactions. RRESP has additional bits for shared read transactions that are indirectly driven by the CRRESP outputs from a snooped master. In addition to the full ACE interface, the AMBA-4 specification also defines ACE-Lite, which has the additional signals on the existing channels but not the new channels. ACE-Lite masters can snoop ACE-compliant masters, but cannot themselves be snooped.
For more details on ACE signaling, refer to Arm ACE protocol specification.
The ACE interface connects to cache coherent interconnect (CCI) and is configurable to support I/O and full coherency.
•I/O coherency though the use of ACE-Lite where I/O-coherent masters can snoop APU caches.
•Full coherency though the use of ACE where fully-coherent masters can snoop each other’s caches.
The two-way coherent S_AXI_ACE_FPD interface uses a 40-bit wide physical address. The ACE port enables the PL-masters to have their caches in PL. The PL-ACE master cannot allocate into the APU L2 cache however, it has coherent access to L2 cache.
If a PL ACE port is not used or used as ACE-Lite, then its snoop channels must be disabled (using the CCI ACCHANNELEN input that is controlled by a LPD_SLCR.LPD_CCI register). This ensures that the CCI does not generate snoop to the PL.
Note: Although the programmable logic (PL) ACE port can be used as an AXI4 interface, Xilinx recommends against this usage.