ACE Interface

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The Zynq UltraScale+ MPSoCs interface to the cache-coherent interconnect (CCI) only supports the AXI coherency extension (ACE). ACE is an extension to the AXI protocol and provides the following enhancements. See PS-PL AXI Interfaces.

Support for hardware cache coherency.

Barrier transactions that ensure transaction ordering.

System-level coherency enables the sharing of memory by system components without the software requirement to perform software cache maintenance to maintain coherency between caches. Regions of memory are coherent if writes to the same memory location by two components are observable in the same order by all components.

The ACE coherency protocol ensures that all masters observe the correct data value at any given address location by enforcing that only one copy exists whenever a store occurs to the location. After each store to a location, other masters can obtain a new copy of the data for their own local cache, allowing multiple copies to exist. Refer to the Arm® AMBA® AXI and ACE protocol specification for a detailed overview.