ACE Interface for Full Coherency

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Full-coherent masters can snoop each other's caches. For fine-grain data sharing between the APU and the PL, a system can have cache implemented in PL. Full coherency is provided through the CCI ACE ports. ACE provides additional signals that allow CCI to request data cached by various masters (APU or PL).

TIP:   For full coherency, transactions can only have a 64-byte cache line size.

 

IMPORTANT:   When using the PL-ACE as an ACE-lite or AXI4 port, you must ensure that the PL master does not generate transactions with burst lengths greater than 16. From the ACE port to the DDR controller, there is an AXI4 path without a mechanism to split longer burst lengths into smaller transactions similar to how they are split by the FIFO-enabled AXI interfaces. Failure to limit transaction burst lengths can lead to lockups on the bus for many cycles, starvation on other DDR ports, and very high latencies observed on other masters in the system.

Note:   A cached PL master connected to the PL-ACE interface, that is required to be in an inner-shareable domain with the APU, should tie-off the BROADCASTINNER signal to 1. This can be done by writing to the LPD_SLCR.LPD_APU register. This tie-off signal must be either High or Low before the APU reset is deasserted.