ACE-Lite Interface for I/O Coherency

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The ACE-Lite interface is a defined subset of the full ACE interface. ACE-Lite is used by master components that do not have hardware coherent caches, but can issue transactions that could be held in the hardware coherent caches of other masters. ACE-Lite enables uncached masters to snoop ACE coherent masters.

The S_AXI_ACE_FPD port can be used as ACE-Lite with some limitations. In addition to providing one way coherency, ACE-Lite can be used to force flush or invalidate an APU cache.

The following describes using S_AXI_ACE_FPD as ACE-Lite.

An ACE slave needs RACK and WACK inputs. But ACE-Lite master does not have RACK and WACK outputs. The PL must drive these signals because they are used to release transactions from the internal trackers in the CCI.

In the CCI, the ACE interface does not support burst splitting. The PL master must ensure that any shareable transactions (ReadOnce, WriteUnique) do not cross a 64-byte boundary. Furthermore, if using a fine-grained interleaving (<4 KB), then the PL master must ensure that no transaction crosses the interleaving boundary.

The ACE DVM [ACCHANNELEN] bit should be set Low (using the LPD_SLCR.LPD_CCI register). This will ensure that requests are never sent on the AC channel of this ACE.

The I/O coherent masters only need to indicate the shareability of a read or write transaction using AxDOMAIN. Other signals, such as AxSNOOP, AxBAR, and AxUNIQUE, can be tied to zero.

ACE-Lite provides I/O coherency-like S_AXI_HPCx_FPD ports. However, ACE-Lite requires physical address, additional signals, and ACE-related restrictions must be followed. Comparably, S_AXI_HPCx_FPD uses a virtual address and is AXI compliant. When possible, using S_AXI_HPCx_FPD is preferred for I/O coherency (instead of ACE-Lite).