The PL masters can also snoop APU caches through the APU accelerator coherency port (ACP). The ACP accesses can be used to (read or write) allocate into L2 cache. However, the ACP supports restricted transactions. See PS-PL AXI Interfaces.
The PL masters can also snoop APU caches through the APU accelerator coherency port (ACP). The ACP accesses can be used to (read or write) allocate into L2 cache. However, the ACP supports restricted transactions. See PS-PL AXI Interfaces.