ACP Coherency

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PL masters can also snoop APU caches through the APU accelerator coherency port (ACP). The ACP accesses can be used to (read or write) allocate into L2 cache. However, the ACP supports restricted transactions. See PS-PL AXI Interfaces.