ACP Limitations

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The ACP accepts only the following (cache-line friendly) transactions.

64-byte aligned (of 64-byte) read/write INCR transactions. All write-byte strobes must be the same for all beats (either enabled or disabled). AxLEN must be 0x03 (four beats).

16-byte aligned (of 16-byte) read/write INCR transactions. Write-byte strobes can have any value. AxLEN must be 0x00 (one beat).

ARCACHE and AWCACHE are restricted to the values 0b0111, 0b1011, and 0b1111.

The value of 0b11 for AxUSER[1:0] is not allowed, other values (0b00, 0b01, 0b10) are allowed.

For further details, see the Arm Cortex®-A53 MPCore Processor Technical Reference Manual [Ref 46].

The ACP interface supports up to four outstanding transactions. These can be any combination of reads and writes. However, there can only be one outstanding transaction per AXI ID. The master must avoid sending more than one outstanding transaction on the same AXI ID to prevent the second transaction from stalling the interface until the first is complete.