The ACP provides a low-latency path between the PS and the accelerators implemented in the PL when compared with a legacy cache flushing and loading scheme. Steps that must take place in an example of a PL-based accelerator are as follows.
1.The CPU prepares input data for the accelerator within its local cache space.
2.The CPU sends a message to the accelerator using one of the HPM AXI master interfaces to the PL.
3.The accelerator fetches the data through the ACP, processes the data, and returns the result through the ACP.
4.The accelerator sets a flag by writing to a known location to indicate that the data processing is complete. The status of this flag can be polled by the processor or can generate an interrupt.
When compared to a tightly-coupled coprocessor, ACP access latencies are relatively long. Therefore, ACP is not recommended for fine-grained instruction level acceleration. Instead, for coarse-grain acceleration, such as video frame-level processing, ACP does not have a clear advantage over traditional memory-mapped PL acceleration because the transaction overhead is small relative to the transaction time, and can potentially cause undesirable cache thrashing. Therefore, ACP is optimal for medium-grain acceleration, such as a block-level crypto accelerator and video macro-block level processing.
The ACP port supports limited throughput (four outstanding transactions), two transaction burst lengths (64-byte and 16-byte), and adversely affects CPU cluster performance (by treating all ACP transactions as coherent).
RECOMMENDED: For the best power and performance, AMD recommends using either an S_AXI_HPCx_FPD port or the ACE port to provide I/O coherency as the preferred approach over ACP.
CAUTION! Avoid the use of the ACP in security/safety critical applications requiring isolation within the APU and/or between PS and PL. The ACP, if enabled, has unrestricted access to the entire L2 cache of the APU and untrusted IP in the PL can make itself appear secure by modifying its AxPROT bits. If the ACP is used in this system, two precautions are highly recommended. The first, is to wrap any IP in the PL that has ACP access with trusted security logic that controls the AxPROT bits rather than allowing the IP to do so. The second is to ensure that access to the entirety of L2 cache by this IP does not violate the system security goals.