AHCI SATA Configuration

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Table 32-8:      AHCI SATA Configuration

Task

Register

Bit Field

Register Offset

Bits

Value

Program command list base address

SATA_AHCI_PORTCNTRL.PxCLB

[CLB]

0x0100

31:10

Address of CLB data structure

Program FIS base address

SATA_AHCI_PORTCNTRL.PxFB

[FB]

0x0108

31:8

Address of FIS data structure

Enable FIS receive

SATA_AHCI_PORTCNTRL.PxCMD

[FRE]

0x0118

4

'b1

Wait until [CR] (bit 15) bit set in register SATA_AHCI_PORTCNTRL.PxCMD to make sure no command list is running.

Start command processing

SATA_AHCI_PORTCNTRL.PxCMD

[ST]

0x0118

0

b'1