APU Coherent Interfaces

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

S_AXI_HPC0_FPD and S_AXI_HPC1_FPD can optionally support I/O coherency to the APU’s L1 and L2 caches as these interfaces connect to the cache coherent interconnect (CCI). These ports can snoop APU caches through CCI provided ports. This avoids the need for software to provide coherency by flushing APU caches when APU data is shared with the I/O masters. Hardware managed I/O coherency simplifies software, improves system performance, and reduces power. Because both the S_AXI_HPC0_FPD and S_AXI_HPC1_FPD interfaces are routed through the CCI before reaching the DDR memory controller, these two ports have a longer latency to DDR.

 

RECOMMENDED:   Set the AxCACHE bits appropriately to enable snooping into APU caches. Drive any non-zero value on AxCACHE[3:2] for coherency; AxCACHE[3:2] = 2’b00 indicates a non-coherent transaction. Snooping should also be enabled by writing to the appropriate registers in the CCI. The Snoop_Control_Register_S3[Enable_snoops] bit should be set to generate a snoop request to the APU ACE interface.

For further details on coherency through CCI refer to Arm's CCI TRM.