APU Core Power Up

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Unlike power down, powering up an APU core is typically requested either by another CPU through power-up request registers on the PMU or by interrupts that are associated with the peripherals on the powered-down APU core. For the latter, the interrupts for these peripherals are passed to the PMU when the ACPU is powered down. For power up, follow these steps.

For powering up an APU core, the particular bit in the REQ_PWRUP_TRIG global register has to be set by the requesting device. For the description of REQ_PWRUP_TRIG global register, see the Register Overview section.

If a direct power-up or wake by the GIC is associated with the APU core, the PMU follows the steps as specified by the ROM code and powers up the APU. A direct power-up refers to a power-on event triggered by an interrupt destined for the APU core, as opposed to software triggering the event by writing to the request register in the PMU_GLOBAL module.

If a direct wake up or wake by GIC occurs after the power-up is completed, the reset to the APU core is also released automatically.

If the power-up request is made by another processor, the same processor has to explicitly request for the reset to the APU core be released through the PMU reset-request register.

Check if the appropriate bit position in the REQ_PWRUP_STATUS global register is set to 0 to indicate that the power up request is served by the PMU.

 

IMPORTANT:   After the power-up, the CPUPWRDWNREQ field of the PWRCTL register in the APU contains the value of 1 as the power status for the core that is just powered up. The CPU is expected to check the register, upon boot, to identify if this was a cold boot or a wake from sleep. Post-verification, the processor is expected to clear the bit in the CPUPWRDWNREQ field of the PWRCTL register.