APU Core Private Physical and Virtual Timers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The system timer is documented in the Cortex-R5F or Cortex-A53 MPCore TRMs [Ref 46] [Ref 48]. The clock is controlled by the CRL_APB.DBG_TSTMP_CTRL register Vivado PCW [DBG_TSTMP] setting.