APU Interrupt Grouping and Virtualization

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

A virtual machine running on a processor communicates with a virtual CPU interface on the GICv2 (This Figure). The virtual machine receives virtual interrupts from this interface, and cannot distinguish these interrupts from physical interrupts.

A hypervisor handles all IRQs, translating those destined for a virtual machine into virtual interrupts, and, in conjunction with the GIC, manages the virtual interrupts and the associated physical interrupts. It also uses the GIC virtual interface control registers to manage the virtual CPU interface. As part of this control, the hypervisor updates the List registers that are a subset of the GIC virtual interface control registers. In this way the hypervisor and GIC together provide a virtual distributor that appears to a virtual machine as the physical GIC distributor.

The GIC virtual CPU interface signals virtual interrupts to the virtual machine, subject to the normal GIC handling and prioritization rules.

Secure software assigns the following.

°Secure interrupts to group 0, signaled to the processor as FIQs

°Non-secure interrupts to group 1, signaled to the processor as IRQs.

A hypervisor is used for the following.

°Implements a virtual distributor, using features of the virtualization extension on the GIC. This virtual distributor can virtualize IRQ interrupts from the GIC as virtual IRQ and virtual FIQ interrupts, which it routes to an appropriate virtual machine.

°Routes physical IRQs to hypervisor mode, so they can be serviced by the virtual distributor.

When the GIC signals an IRQ to the processor, the interrupt is routed to hypervisor mode. The hypervisor determines whether the interrupt is for itself or for a guest OS. If it is for a guest OS it determines the following.

The specific guest OS that must handle the interrupt.

Whether that guest OS has configured the interrupt as an FIQ or as an IRQ

The interrupt priority, based on the priority configuration by the target guest OS.

If the interrupt targets the current guest OS, the hypervisor updates the list registers, to add the interrupt to the list of pending interrupts for the current virtual machine.

Figure 13-3:      APU with Interrupt Virtualization Block Diagram

X-Ref Target - Figure 13-3

X15329-GICv2.jpg

Note:   The APU GIC is physically located on the AXI interconnect as an FPD slave, but should only be accessed by the APU MPCore. The FPD main interconnect switch can restrict access to the APU GIC. However, a PL master can access the APU GIC through the S_AXI_ACP_FPD interface and cannot be stopped by the FPD switch. The XMPU can be configured to block the S_AXI_ACP_FPD interface from accessing the APU GIC.