APU Interrupt Partitioning

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

This section covers the partitioning of the GICv2.

The distributor block performs interrupt prioritization and distribution to the CPU interface blocks that connect to the processors in the system.

Each CPU interface block performs priority masking and preemption handling for a connected processor in the system.

The GIC virtualization extensions add a virtual CPU interface for each processor in the system. Each virtual CPU interface is partitioned into the following blocks.

Virtual interface control: The main component of the virtual interface control block is the GIC virtual interface control registers. These registers include a list of active and pending virtual interrupts for the current virtual machine on the connected processor. Typically, these registers are managed by the hypervisor that is running on that processor.

Virtual CPU interface: Each virtual CPU interface block provides physical signaling of virtual interrupts to the connected processor. The Arm processor virtualization extensions signal these interrupts to the current virtual machine on that processor. The GIC virtual CPU interface registers, accessed by the virtual machine, provide interrupt control and status information for the virtual interrupts.