APU MPCore System Counter

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The system timer is documented in the Cortex-A53 MPCore Technical Reference Manual. This counter is sometimes referred to as the global counter. The counter is controlled by IOU_SCNTRS register set. The clock controlled by CRL_APB.TIMESTAMP_REF_CTRL register; Vivado PCW [TIMESTAMP] setting.