APU Power Management

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The Cortex-A53 MPCore processor provides mechanisms and support to control both dynamic and static power dissipation. The individual cores in the Cortex-A53 processor support four main levels of power management. This section describes the following.

Power Islands

Power Modes

• Event communication using a wait for event (WFE) or a send event (SEV) instruction. See Table: PL Event Signals.

• Communication with the platform management unit (PMU). See Platform Management Unit.