APU Private Interrupts

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Each APU core has a private set of peripheral interrupts routed from the CPU itself and the PL. They are listed in Table: APU Private Peripheral Interrupts.

Table 13-4:      APU Private Peripheral Interrupts

Name

Interrupt ID

Description

Virtual maintenance interrupt

25

Configurable event generated by virtual CPU interface to indicate a situation that might require hypervisor action.

Hypervisor timer

26

Physical timer event in hypervisor mode, PPI5 (CNTHP IRQ).

Virtual timer

27

Virtual timer generated event, PPI4 (CNTV IRQ).

Legacy FIQ signal

28

FIQ signal from the PL.

Secure physical timer

29

Secure physical timer event, PPI1 (CNTPS IRQ).

Non-secure physical timer

30

Non-secure physical timer event, PPI2 (CNTPNS IRQ).

Legacy IRQ signal

31

IRQ signal from the PL.