A processor element is in hypervisor mode when it is executing at EL2 in the AArch32 state. An exception return from hypervisor mode to software running at EL1 or EL0 is performed using the ERET instruction.
EL2 provides a set of features that support virtualizing the non-secure state of an Arm v8-A implementation. The basic model of a virtualized system involves the following.
•A hypervisor software, running in EL2, is responsible for switching between virtual machines. A virtual machine is comprised of non-secure EL1 and non-secure EL0.
•A number of guest operating systems, that each run in non-secure EL1, on a virtual machine.
•For each guest operating system, there are applications that usually run in non-secure EL0, on a virtual machine.
The hypervisor assigns a virtual machine identifier (VMID) to each virtual machine. EL2 is implemented only in a non-secure state, to support guest operating system management.
EL2 provides information in the following areas.
•Provides virtual values for the contents of a small number of identification registers. A read of one of these registers by a guest operating system or the applications for a guest operating system returns the virtual value.
•Traps various operations, including memory management operations and accesses to many other registers. A trapped operation generates an exception that is taken to EL2.
•Routes interrupts to the appropriate area.
°The current guest operating system.
°A guest operating system that is not currently running.
In a non-secure state the following occurs.
•The implementation provides an independent translation regime for memory accesses from EL2.
•For the EL1 and EL0 translation regime, address translation occurs in two stages.
°Stage 1 maps the virtual address (VA) to an intermediate physical address (IPA). This is managed at EL1, usually by a guest operating system. The guest operating system believes that the IPA is the physical address (PA).
°Stage 2 maps the IPA to the PA. This is managed at EL2. The guest operating system might be completely unaware of this stage. Hypervisor creates the stage 2 translation table.
This Figure shows the Arm v8 execution modes discussed in this section.
Note: The following notes refer to This Figure.
1.AArch64 is permitted only if EL1 is using AArch64.
2.AArch64 is permitted only if EL2 is using AArch64.
The hypervisor directly controls the allocation of the actual physical memory, thereby fulfilling its role of arbiter of the shared physical resources. This requires two stages (VA®IPA, and IPA®PA) of address translation. This Figure shows the traditional versus virtualized systems addresses in the translation stage.