AUX Read Transaction

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The AUX read transaction (This Figure) is prepared by writing the transaction address to the AUX_ADDRESS register. After it is set, the command and the number of bytes to read are written to the AUX_COMMAND register. After initiating the transfer, the host should wait for an interrupt or poll the INTERRUPT_STATUS register to determine when a reply is received. When the REPLY_RECEIVED signal is detected, the host can read the requested data bytes from the AUX_REPLY_DATA register. This register provides a single address interface to a byte FIFO which is 16 elements deep. Reading from this register automatically advances the internal read pointers for the next access.

Figure 33-21:      AUX Read Transaction

X-Ref Target - Figure 33-21

X15511-aux-read-flow.jpg