AXI Bus Master

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Transfer size is set to 64-bit words using the AXI bus width select bits in the network configuration register, and burst size can be programmed to single access or bursts of 4, 8, 16, or 256 words using the DMA configuration register.

The DMA memory transactions will be routed to the CCI.