The AXI-PCIe bridge is a protocol converter between the AXI3 and PCIe domains and also provides optional DMA capability.
When a remote master issues a transaction over PCIe link, it appears as an AXI transaction on the AXI master port. When a local master (in the PS) issues an AXI transaction on the slave port, it goes onto the PCIe link based on address translation apertures set as either memory or configuration TLP.
The bridge supports non-contiguous and zero-byte enable in compliance with the PCIe specification. For the AXI master the following is true.
•On AXI, a 1DW or 2DW write from the PCIe domain received with a non-contiguous byte enable is completed as a series of 1 byte writes only for the enabled bytes.
•PCIe zero-byte writes are propagated over AXI as writes with no byte enables asserted.
•PCIe reads with non-contiguous byte enables are converted to AXI reads reading all bytes. Disabled bytes are read and data is provided as part of the completion data. AXI memory, which can be the target of such non-contiguous reads, should be prefetchable and should not have any read side-effects.
•PCIe zero-byte reads are issued as a single byte read in the AXI domain and provided as completion data. This provides the desired write-flushing mechanism.
•Writes use the same AXI ID (m_awid, m_wid, m_bid) for all write transactions regardless of the source; hence, these should be completed in order on AXI.
•Read and write response timeouts are configurable through registers in the bridge.
°Reads initiated by the master AXI that do not complete within the specified timeout period are assumed to never complete and result in a completer abort response on the PCIe link.
°Writes initiated by the master AXI that do not complete within the specified timeout period are assumed to never complete and are terminated.
For the AXI slave the following is true.
•An AXI write with non-contiguous byte enable is completed with as many contiguous byte-enable write transactions as necessary to write all enabled bytes in the PCIe domain and then is provided with an aggregated write response.
•Transactions that cannot be forwarded to the PCIe due to PCIe specific reasons (such as the PCIe data link layer is down, PCIe domain is in reset, or when bus master enable = 0 for Endpoint applications) are dropped and completed on AXI with a DECERR status.
•AXI slave interface initiated reads, I/O writes, and configuration writes that fail to complete after a timeout duration are assumed to never complete and are terminated with a SLVERR response to the AXI. When the AXI clock is 250 MHz, the duration of the timeout is 50 ms. The timeout has a linear relation with the AXI clock, for example, the timeout is 100 ms if the AXI clock is 125 MHz. When the integrated block for PCIe completion timeout disable attribute is set to one, the timeout is disabled.