AXI-PCIe Transaction Mapping

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Table: Egress Transaction Map summarizes AXI transaction mapping to PCIe domain.

Table 30-5:      Egress Transaction Map

AXI Transaction

PCIe Transaction

Notes

AXI read transaction

Local bridge register read if BREG aperture is hit.

DMA register read if DREG aperture is hit.

Configuration read TLP if ECAM aperture is hit.

Memory read TLP if no other aperture is hit.

For memory read TLP, the address is translated if the egress translation is hit. Otherwise, it remains the same.

AXI write transaction

Local bridge register write if BREG aperture is hit.

DMA register write if DREG aperture is hit.

Configuration write TLP if ECAM aperture is hit.

Memory write TLP if no other aperture is hit.

For memory write TLP, the address is translated if the egress translation is hit. Otherwise, it remains the same.

To generate messages, the AXI-PCIe bridge provides registers. Refer to the AXI_PCIE_MAIN.TX_PCIE_MSG_* registers for details on generating these types of transactions in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].

Note:   Special handling is required by software for memory write transactions with ECRC errors. The PCI Express specification mandates that the ECRC errors be captured and signaled to the software. The error could be in the payload or in the header. If the payload is corrupted, a known location could receive incorrect data. If the address is corrupted, the transaction could end up at a completely incorrect slave. Software is required to read the header from the AER registers in the PCIe configuration space and take corrective action because, by the time software receives notification of such an event, the write transaction with the ECRC error could already be executed.