Acceptance Filter Enable

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The acceptance filter register (AFR) defines the acceptance filters usage. It includes four enable bits that correspond to the four acceptance filters. Each acceptance filter ID register (AFIR) and acceptance filter mask register (AFMR) pair is associated with a use acceptance filter (UAF) bit.

When the UAF bit is 1, the corresponding acceptance filter pair is used for acceptance filtering.

When the UAF bit is 0, the corresponding acceptance filter pair is not used for acceptance filtering.

To modify an acceptance filter pair in normal mode, the corresponding UAF bit in this register must first be set to 0. After the acceptance filter is modified, the corresponding UAF bit must be set to 1 for the filter to be enabled.

The UAF bits in the can.AFR register enable the RX acceptance filters.

If all UAF bits are set to 0, then all received messages are stored in the RXFIFO.

If the UAF bits are changed from a 1 to 0 during reception of a CAN message, the message will not be stored in the RXFIFO.

If any of the enabled filters (up to four) satisfy the following equation, then the RX message is stored in the RXFIFO.

If (AFMR and Message_ID) == (AFMR and AFIR) then capture message

Each acceptance filter is independently enabled. The filters are selected by the can.AFR register.

Set can.AFR[UAF4] = 1 to enable AFMR4 and AFID4.

Set can.AFR[UAF3] = 1 to enable AFMR3 and AFID3.

Set can.AFR[UAF2] = 1 to enable AFMR2 and AFID2.

Set can.AFR[UAF1] = 1 to enable AFMR1 and AFID1.

If all can.AFR[UAFx] bits are set to 0, then all received messages are stored in the RXFIFO. The UAF bits are sampled by the controller at the start of an incoming message.