Accessing Bridge Internal Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Internal bridge registers are accessed through the AXI slave using a bridge register translation. Various registers like the DMA registers, MSI-X table, and pending-bit array are accessed through their respective translations. The various translation registers are listed in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].

The MSI-X table and PBA are applicable only for Endpoint mode of operation and the corresponding registers are implemented in the AXI-PCIe bridge at predefined offsets.

The bridge register translation on exit from reset is configured to accept all AXI transactions as bridge register access. As part of the Zynq UltraScale+ MPSoC initialization, one of the actions should be to reconfigure the bridge register translation into a specific (small) window to enable other address translations like DMA registers or ECAM. Refer to the Bridge Initialization section of the programming model for further details.

 

IMPORTANT:   The recommended address values, as defined in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4], should be used for various apertures. All access to the bridge registers should be one DWORD (32 bits) from the AXI domain.

This Figure shows the AXI and PCIe domain access of various registers in the AXI-PCIe bridge.

Figure 30-4:      AXI-PCIe Bridge Register

X-Ref Target - Figure 30-4

X15488-axi-pcie-bridge-register.jpg