Additional Measures

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Safety features for the non-LPD Zynq UltraScale+ MPSoC components include:

DDR interface supports ECC for 32-bit and 64-bit words

°Double error detection

°Single error correction

ECC support for APU L2, L1-D memories

Parity support for APU L1-I memories

QOS management

°QOS controls on masters

°QOS management in PS AXI

°QOS management in PS DDR controller

PL or multi APU cores can provide redundant processing

All FPD memories can be tested at full processing speed during boot by MBIST

Leverage of PL for implementation of safety features

°Provides HFT channel capability

°Provides error logging

°PL can remain active if PS is reset due to error