Additional References

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2023-12-21
Revision
2.4 English

56.Recommendation for Applications Using Approved Hash Algorithms

57.SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions

58.Zynq UltraScale MPSoC Cache Coherency

59.System Software Mutexes on Zynq UltraScale

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

12/21/2023

2.4

Chapter 1: Corrected This Figure to correct the mismatch of QoS Regulator port numbers from 5,6,7,2,3,4 to 1,2,3,4,5,6. Revised Table: Device ID Codes and Minimum Production Revisions to include ID codes for the ZU63, ZU64, and ZU3T devices.

Chapter 2: Corrected description for power pins VCC_PSDDR_PLL, VCC_PSINTFP_DDR, and VCCO_PSDDR in Table: Power Pins. Modified the description of pin PS_PROG_B as input/output in Table: Clock, Reset, and Configuration Pins.

Chapter 6: Modified This Figure to include a connection from APB to RAM.

Chapter 8: Revised Table: IEC61508:2010 Functional Safety Integrity Addressed by Zynq UltraScale+ to include FPD and modified the description of PL.

Chapter 11: Modified the description of the BootROM error codes 0x36 as non-secure and included 0x39 in Table: BootROM Error Codes. Revised Table: PL Bitstream Length to include ID codes for ZU63, ZU64, and ZU3T devices.

Chapter 12: Corrected abbreviation from LBD to LPD for LPD_SC and from FBD to FPD for FPD_SC in Table: Zynq UltraScale+ MPSoC Security eFUSEs.

Chapter 13: Corrected description of IRQ Name FPD_XMPU from memory to DDR.

Chapter 14: Modified This Figure to include an additional mux of clock source. Updated bits 11:9 for offset 0x00 and changed the description to zero (sbz) Table: SWDT Register Overview.

Chapter 15: Corrected This Figure for a mismatch of QoS Regulator port numbers from 5,6,7,2,3,4 to 1,2,3,4,5,6.

Chapter 16: Corrected This Figure for a mismatch of QoS Regulator port numbers from 5,6,7,2,3,4 to 1,2,3,4,5,6.

Chapter 17: Corrected This Figure for a mismatch of QoS Regulator port numbers from 5,6,7,2,3,4 to 1,2,3,4,5,6. Added a note to Table: DDR Memory Controller Conditions for clarity on the number of row address bits. Corrected Table: Example Memory Configurations for the number of components for LPDDR4 with x32 with DDP from 2 to 1, corrected the link for Answer Record 67330.

Chapter 23: Corrected the term [RX_OVERFLOW] to [TX_OVERFLOW] in TXFIFO under Functional Description.

Chapter 26: Note added regarding DLL_REF_CLK for TX and RX clock delay.

Chapter 28: Added Table: EMIO when PS only Reset for the state of each EMIO for PS only reset.

Chapter 32: Corrected the term from port to controller in the first feature.

Chapter 34: Added a note regarding GEM RX clock under Clock Domains. Corrected This Figure for tx_r_data. Added note regarding UDP under IEEE Std 1588 Time Stamp Unit. Included information on gem_tsu_inc_ctrl[1:0] under Precision Time Protocol via EMIO. Corrected the term IOU_SWITCH_CLK to LPD_LSBUS_CLK under Configure the PHY. Changed the frame rate from 2K to 4K in Video Code Unit Features for 8 bit and 10 bit color depth.

Chapter 37: Added information to CSU Clock Generators. Corrected the program counter values in Clock Monitor Programming Example from 0000_0000h to 0000_8000, 0001_028Ah to 0001_028Fh, and 0000_FD76h to 0000_FD70h. Added Table: PLL Programming Data for Fractional Feedback Divider Values for PLL programming values when the PLL is in fractional mode. Note added for PS_REF_CLK.

Chapter 39: Corrected ARM DAP IR MSB from 5 to 3 in This Figure. Updated the MBIST section. Updated the LBIST covered list. Note added for Table: Scan Clear TRIG and ACK Register Bit Fields regarding MBIST and Scan clear.

1/04/2023

2.3.1

Version 2.3 revision history updated to expand on changes made.

9/15/2022

2.3

Chapter 1: Corrected the RPU block connection in This Figure. Revised Table: Device ID Codes and Minimum Production Revisions to include IDCODEs for ZU1, ZU42, ZU65, and ZU67 devices.

Chapter 2: Revised Table: Power Pins to include PS_REF_CLK for pin VCCO_PSIO[0:3]. Table: Clock, Reset, and Configuration Pins revised to include a reference to the TPOR specification. Updated the description for HP in Table: PS-PL AXI Interfaces Summary. Chapter 3: Added note for clarification to System Memory Virtualization Using SMMU Address Translation using SMMU address translation.

Chapter 4: Added reference to switches in This Figure.

Chapter 6: Revised This Figure to include error aggregator module block. Table: PMU Error Sources and Reset State Masks updated to define Bits [21:18] as PMU firmware interrupt bits.

Chapter 7: Renamed PS SYSMON signal to PS SYSMON sensor in This Figure.

Chapter 8: Updated Introduction to include certification for ISO 26262:2018 and IEC 61508:2010 based applications for LPD, FPD, and PL domains.

Chapter 9: Note added to Table: PL SYSMON Sensor Channels to address PL Sysmon initiation.

Chapter 10: Corrected address from 1 GB 0x400_0000 to 1 GB 0x4000_0000 in This Figure. Table: CPU Private Registers updated to include GPV register information. Added information on system software mutexes to System-level Control Registers.

Chapter 11: Updated the gray key in Table: Boot Header Format. Added a description for error code 0x3F in Table: BootROM Error Codes. Missing ZU1 device details added to Table: PL Bitstream Length. Updated device names (XCZUx to ZUx) and removed in details of ZU58 and ZU59 parts in Table: PL Bitstream Length. ROM support updated in Table: Register Access Range and Boot Mode.

Chapter 12: Updated Key Management to provide more information on the device key. Replaced PPK0_0 and PPK1_0 with PPK{0,1} and size of PPK1_0 changed from 32 to 384 in Table: Zynq UltraScale+ MPSoC Security eFUSEs. Integration and Test Support (BH RSA Option) updated on BH RSA option.

Chapter 13: Defined IDCICR in Table: System Interrupts. IPI message buffers for channel numbers 0, 1 and 2 corrected in Table: IPI Channel and Message Buffer Default Associations.

Chapter 15: Corrected IOP Bus Masters section and added notes to expand on the AXI Performance Monitor section. Master AXI reset signal moved inside the AXI master block in This Figure. The term position replaced with port and included the information about Qos_Control_Register_S2 in Table: QoS Regulators Mapping.

Chapter 16: Corrected connection from LPD Main Switch to RPU switch for port S0 of the DDR memory controller in This Figure. Updated XMPU Regions, Region Checking Operation, Configuration, and XPPU Self-Protection. Corrected System Masters for DDR XMPU0 to RPU in Table: System Protection Units. Included SMMU TCU and CCI in Table: Master IDs List. Value written to OCM_XMPU_CFG. R00_END register is changed from 0F_D0CFh to 0F_FFCFh in the Program the OCM XMPU section.

Chapter 17: Revised This Figure to correct the connection from the LPD main switch to port S0 of the DDR memory controller. Table: DDR Memory Controller Conditions updated to state 3DS DDR4 is not supported in PS. XMPU0 connection updated from RPU and LPD Masters to RPU

9/15/2022

2.3 (cont’d)

This Figure. Updated Power and Reset, ECC Programming Model, and Programming Topics.

Chapter 19: Updated Introduction to address memory to I/O buffer transfers. Added new section Total Transferred Bytes Overflow.

Chapter 20: Assign MIO Pin to CAN TX Output section 0 has been replaced by 1 for BANK1_CTRL6 [22] bit in step 3 of Programming Example – Assign MIO Pin to CAN TX Output.

Chapter 23: Corrected the data written to TX FIFO from 32 bits to 8 bits in Table: SPI Interrupt Handler. Corrected AR7358 hyperlink.

Chapter 24: Removed descriptions for IOP transactions in the DMA–AXI Master section.

Chapter 25: Removed descriptions for IOP transactions in the AXI Master Interface.

Chapter 26: FIFO buffer size is hard coded and does not have any software control, FIFO Buffer section revised to address this. Removed IOP transaction descriptions in the PIO/DMA Controller section. Corrected the Block Buffer section to address the size of the hard coded block buffer. Receive Clock Tap Delay section updated with sd{0,1}_itapdlyena. SD Interface Voltage Translation updated to include a note addressing the SDx_DIR0 and SDx_DIR1 direction signals. Revised This Figure to include the voltage level shifter. Table: SD Clock Frequency Change updated to reflect the SD3.0 specification.

Chapter 28: Updated ulpi_clk_in_0 to ulpi_clk_in_1 and changed the block color to purple from green in Table: Non-DLL Mode Frequencies.

Chapter 29: Updated PS_MGTREFCLK0, PS_MGTREFCLK1,PS_MGTREFCLK2, and PS_MGTREFCLK3 in the Reference Clock Network section. Added note to Table: Reference Clock per Protocol to address GTR reference clock PS_MGTREFCLKP/N.

Chapter 31: PHY Loopback updated to address the external USB2.0 ULPI PHY RESET (ULPI_PHY_RESETB) signal.

Chapter 33: Removed DP_MAIN_STREAM_POLARITY information from Table: DisplayPort Configuration Registers.

Chapter 34: GEM does not support PL checksum offloading, GEM Features section updated accordingly. Corrected tx_r_valid signal in This Figure. Removed descriptions for IOP transaction in the DMA Controller section. Note added to address RX pause frame not being supported in the PFC Pause Frame Reception section. Configure the PHY section updated to replace IOU_SWITCH_CLK with LPD_LSBUS_CLK. Removed duplicate step from the Receive Buffer Descriptor List section.

Chapter 35: Connection from the LPD Main Switch to port S0 changed to RPU switch to port S0 of the DDR memory controller in This Figure, This Figure, This Figure, Table: PS-PL Interrupts Summary. Corrected interface S_AXI_HPM{0,1}_FPD to M_AXI_HPM{0,1}_FPD in This Figure. Added description to interface S_AXI_HPC{0,1}_FPD in Table: PS-PL Interface Summary. Table: PS-PL Interrupts Summary updated to include interrupts reference.

Chapter 37: Corrected value of CHKRx_CLKA_LOWER [thrshld} in Clock Monitor Programming Example from 0000_FD76Fh to 0000_FD76h. Revised Table: LPD Peripheral Clock Control to correct addresses for SPI(0/1)_REF_CTRL and UART(0/1)_REF_CTRL. DP_VIDEO_REF_CTRL [SRCSEL] reset state corrected to DPLL from VPLL.

Chapter 39: Information related to critical-function blocks removed from LBIST section and a note has been added to address the logic in the crypto engines.

12/04/2020

2.2

Chapter 1: Revised This Figure, Table: Device ID Codes and Minimum Production Revisions, and Table: System Features Assigned by Software.

Chapter 2: Table: Power Pins and Table: Clock, Reset, and Configuration Pins.

Chapter 4: Revised Table: RPU Pin Configuration and TCM Access from a Global Address Space.

Chapter 6: Revised.

Chapter 11: Revised.

Chapter 12: Revised.

Chapter 13: Revised.

Chapter 14: Revised Event Streams, Generic Timer Programming, Event Control Timer Operation, System Watchdog Timers, Table: MIO – EMIO Signals,

Chapter 15: Revised This Figure, Programming, Table: APM Units, Register Overview, Table: QoS Regulators Mapping

Chapter 16: Revised Table: , added Table: CCI Registers

Chapter 17: Revised section and added Dynamic DDR Configuration section.

Chapter 18: Revised Features.

Chapter 19: Revised Simple DMA Mode, Scatter Gather DMA Mode and Rate Control sections.

Chapter 23: Revised the Clocks section and Table: SPI Set Options.

Chapter 24: Revised Quad-SPI Feedback Clock, Table: Generic FIFO Details, Quad-SPI Tap Delay Values

Chapter 25: Revised This Figure and This Figure.

Chapter 26: Revised Table: SDIO Interface Signals.

Chapter 28: Revised Default Logic Levels section. Added Table: MIO Interfaces.

Chapter 29: Revised Features, Table: TX Configurable Driver Attributes, Receiver Termination

Chapter 30: Revised the Bridge Initialization section.

Chapter 31: Revised USB Controller Features, Register Overview, Table: Groups of Register Map

Chapter 32: Revised Features and This Figure.

Chapter 33: Revised Table: PS-PL Signals for the Live Video Interface, Audio Metadata, DisplayPort DMA, CRC Field, and Table: DPAUX Interface Signals.Chapter 34: SGMII, 1000BASE-SX, or 1000BASE-LX, RX Buffers, IEEE Std 1588 Time Stamp Unit, and Table: Ethernet GMII/MII Interface Signals via EMIO Interface. Added Precision Time Protocol via EMIO and Priority Queuing

Chapter 35: Revised Table: AXI Interfaces and Associated Registers and Table: PS-PL AXI Interfaces.

Chapter 37: Revised Choosing a Programmable Logic Interface and Table: System PLL Clock Control Register Settings.

Chapter 38: Revised Table: Resets and RPU Reset Sequence. Added PL Configuration Reset.

Chapter 39: Revised This Figure, MBIST, LBIST, and Scan Clear (Zeroization), and Table: Scan Clear TRIG and ACK Register Bit Fields

8/21/2019

2.1

 

Chapter 12: Revised Encrypt Only Secure Boot Details section.

Chapter 15: Revised the QoS Regulator section. Updated This Figure.

7/22/2019

2.0

Chapter 1: Revised the JTAG IDCODE section.

Chapter 4: Revised the RPU Pin Configuration section.

Chapter 5: Revised the Programming the GPU. Note updated.

Chapter 6: Revised Full-Power Operation Mode section, Table: Global Registers and added Table: Deep-sleep Configuration.

Chapter 11: Revised Boot Modes section, PL Bitstream section and added Table: Register Access Range and Boot Mode.

Chapter 12: Revised Secure Lockdown, SHA-3/384, Boot Operation, Encrypt Only Secure Boot Details, and Loading Bitstreams sections.

Chapter 14: Revised APU Core Private Physical and Virtual Timers and Watchdog Enabled on Reset sections.

Chapter 15: Revised Programming and PS Instances sections.

Chapter 17: Revised Table: DDR Memory Controller Conditions and PHY Description section.

Chapter 20: Revised RX/TX Bit Timing Logic section.

Chapter 24: Revised Reference Clock and Quad-SPI Interface Clocks, Quad-SPI Feedback Clock, and Quad-SPI Tap Delay Values sections.

Chapter 26: Revised Tuning Unit, RX Clock Delay Unit, and Receive Clock Tap Delay sections.

Chapter 29: Revised the EyeScan Module section.

Chapter 30: Revised the Features section, added a note in Integrated Block for PCI Express section, and added an Important note in Single CPU Control section.

Chapter 33: Revised Table: PS-PL Signals for the Live Video Interface.

Chapter 34: Added a note under Table: TX Status Errors.

Chapter 35: Revised the LPD-PL Interfaces section.

Chapter 39: Revised the Toggle Detect on PSJTAG, PL TAP Controller, Trace Debug, Security, Components sections and updated Table: PS TAP Controller Status Register and Table: MBIST Control Register Bit Fields.

Appendix A: Arm References updated.

1/17/2019

1.9

Chapter 1: Revised This Figure.

Chapter 2: Revised Table: Clock, Reset, and Configuration Pins.

Chapter 3: Revised System Virtualization and Power Modes sections.

Chapter 4: Revised Tightly Coupled Memory Address Map section.

Chapter 6: Revised This Figure, This Figure, Table: PMU General Purpose MIO Pins, MIO Pin Considerations, Table: PMU Error Sources and Reset State Masks, and MIO Signals.

Chapter 7: Revised.

Chapter 8: Entire chapter revised.

Chapter 9: Revised Table: PS SYSMON and PL SYSMON Comparison, Register Sets, and Table: PL SYSMON Unit Register Access Interfaces.

Chapter 11: Revised Table: Boot Modes and Table: Boot Header Format.

Chapter 12: Revised PUF Operations, This Figure, Programming AES-GCM Engine, RSA Accelerator, Security Related eFUSEs, Secure Boot Introduction, Secure Boot Summary, Loading Bitstreams, This Figure, and Secure Boot Image Format. Added Device DNA Identifiers, Initialization Vector Register, Secure Non-Volatile Storage, and Enhanced SPK Revocation. Added note to Table: Zynq UltraScale+ MPSoC Security eFUSEs.

Chapter 13: Revised SPI Interrupt Sensitivity.

Chapter 14: Revised TTC Counter Features, TTC Block Diagram, Table: SWDT I/O Control and Configuration Register Sets, and Table: SWDT Register Overview.

Chapter 15: Revised.

Chapter 16: Revised TBU Instances.

Chapter 17: Table: DDR Memory Controller Conditions, Table: Example Memory Configurations table note added, and added a note after the third item in ECC Poisoning Multi-Purpose Register (DDR4 Only).

Chapter 20: Revised.

Chapter 21: Revised.

Chapter 22: Revised Configure Clocks

Chapter 23: Revised Table: SPI EMIO Signals, This Figure, FIFOs, and Clocks, Resets.

Chapter 24: Revised Clocks and Resets, Table: Generic FIFO Details, Table: Generic Quad-SPI Controller: SPI Mode Commands, Table: Generic FIFO Contents for Read Command, Table: Generic FIFO Contents for Quad I/O Read Command, Table: Generic FIFO Contents for Quad Page Program Command, and Table: Quad-SPI Flash Interface Signals.

Chapter 26: Revised Reference Clock, Interface Controller, DLL Clock Mode, Transmit CMD/DAT Delay, Receive Clock Tap Delay, Table: SD DDR Mode, Table: SD Controller Register Overview, Table: SD Clock Frequency Change, Table: SD Card Initialize, and Table: eMMC Card Initialize.

Chapter 27: This Figure updated.

Chapter 28: Default Logic Levels revised.

Chapter 31: Device Programming revised.

Chapter 33: This Figure and This Figure updated.

Chapter 34: Configure the PHY revised.

Chapter 37: Revised This Figure, This Figure, This Figure, and This Figure.

Chapter 38: Revised Table: Resets to System Elements and FPD Reset Sequence.

8/03/2018

1.8

Chapter 19: Revised

Chapter 20: Revised

Chapter 22: Revised

Chapter 23: Revised

Chapter 24: Revised

Chapter 25: Revised

Chapter 26: Revised

Chapter 27: Revised

Chapter 28: Revised

Chapter 29: Revised

Chapter 30: Revised

Chapter 31: Revised

Chapter 32: Revised

Chapter 33: Revised

Chapter 34: Revised

Chapter 35: Revised

Chapter 36: Revised

Chapter 37: Revised

Chapter 38: Revised

12/22/2017

1.7

Revised Debug Features and added MBIST, LBIST, and Scan Clear (Zeroization).

11/01/2017

1.6

Chapter 1: Revised This Figure. Added This Figure and This Figure. Updated Introduction to the UltraScale Architecture. Added Functional Units and Peripherals, Device ID Codes, IP Revisions, System Software, and, Documentation.

Chapter 2Chapter 2: Revised This Figure. Revised Table: Power Pins, Table: Clock, Reset, and Configuration Pins, Table: MIO Pins, Table: Processor Communications, Table: MIO-EMIO Signals and Interfaces, Table: Miscellaneous Signals and Interfaces, Table: Clock Signals, and Table: Timer Signals. Added Table: PS-PL AXI Interfaces Summary and Table 2-14.

Chapter 3: Revised Application Processor Unit Register Overview and This Figure.

Chapter 5: Revised Introduction, Graphics Processing Unit Level 2 Cache Controller, and Graphics Processing Unit Programming Model.

Chapter 6: Revised Introduction. Updated Table: Minimum and Typical Configurations for the Low-Power Mode and This Figure. Revised This Figure and This Figure.

Chapter 7: Revised Introduction and Functional Description. Updated This Figure, This Figure, and This Figure. Added Interfaces and Signals. Revised Table: RTC Register List.

Chapter 9: Revised entire chapter, including changing chapter name.

Chapter 10: Revised This Figure. Updated Table: Top-Level System Address Map. Updated System Address Register Overview. Added Table: PS System Register Map (FPD).

Chapter 11: Updated Introduction, Boot Image Format, and Functional Units. Revised Table: Boot Modes. Updated This Figure and This Figure. Added CSU BootROM Error Codes and PL Bitstream.

Chapter 12: Updated Device and Data Security and Secure Boot. Revised This Figure, This Figure, and This Figure.

Chapter 13: Revised Introduction, System Interrupts, IPI Interrupts and Message Buffers, CPU Private Peripheral Interrupts, and Programming Examples. Updated This Figure and This Figure. Added This Figure.

Chapter 14: Revised APU Core Private Physical and Virtual Timers and System Watchdog Timers.

Chapter 15: Updated Block Diagram, AXI Performance Monitor, Quality of Service, and Interconnect Register Overview. Revised This Figure. Added ATB Timeout Description and Programming Example – Metric Counter. Updated This Figure and This Figure.

Chapter 16: Revised Introduction, TrustZone, SMMU Protection on CCI Slave Ports, XMPU Protection of Slaves, and XPPU Protection of Slaves. Added XMPU Register Set Overview, XPPU Register Set Overview, Programming Example, and Write-Protected Registers Table. Revised This Figure, This Figure, This Figure, and This Figure. Added This Figure, This Figure, and This Figure.

Chapter 17: Revised This Figure, This Figure, This Figure, and This Figure. Updated Introduction, DDR Subsystem Functional Description, Debugging PS DDR Designs, DDR Memory Controller Register Overview, and DDR Memory Controller Programming Model.

11/01/2017

1.6 (cont’d)

Chapter 18: Revised This Figure and updated On-chip Memory Programming Model.

Chapter 19: Updated Introduction, DMA Controller Functional Description, DMA Data Flow, DMA Programming for Data Transfer, and DMA Programming Model for FCI. Updated This Figure.

Chapter 21: Revised This Figure and This Figure. Added This Figure, This Figure, This Figure, This Figure, This Figure, This Figure, and This Figure. Added MIO – EMIO Signals.

Chapter 22: Revised This Figure and This Figure. Updated I2C Controller Functional Description, I2C Controller Register Overview, and I2C Controller Programming Model.

Chapter 23: Revised This Figure. Updated Introduction and Programming Model.

Chapter 24: Revised This Figure, This Figure, This Figure, and This Figure. Updated Introduction, System Control, Generic Quad-SPI Controller, Legacy Quad-SPI Controller, Register Overview, Programming and Usage Considerations, Generic Quad-SPI Controller Programming, and Legacy Quad-SPI Controller Programming.

Chapter 25: Revised Introduction, Functional Description, and NAND Memory Controller Register Overview. Added Clocks and Resets.

Chapter 26: Updated Introduction, Functional Description, and SD/SDIO/eMMC Controller Programming Model. Revised This Figure and This Figure.

Chapter 27: Updated Functional Description and Programming Model.

Chapter 28: Updated MIO Table at a Glance and Register Overview.

Chapter 29: Renamed chapter. Revised Introduction, Functional Description, Register Overview, and Configuration Program. Updated This Figure, This Figure, and This Figure.

Chapter 34: Renamed chapter. Revised Introduction, Functional Description, and Programming Model. Revised This Figure and This Figure through This Figure.

Chapter 35: Renamed chapter. Revised Introduction, Functional Description, Choosing a Programmable Logic Interface, PS-PL Miscellaneous Signals, Processor Event Signals, and Register Overview. Revised This Figure, This Figure, This Figure, This Figure, This Figure, and This Figure.

Chapter 36: Updated Introduction, PL System Monitor, PL System Monitor, PL System Monitor, Video Codec Unit, GTH and GTY Transceivers, and Interlaken.

Chapter 37: Renamed chapter. Revised Introduction and Register Overview. Added System PLL Units, Basic Clock Generators, Special Clock Generators, Programming Examples, PLL Integer Divide Helper Data Table, System PLL Control Registers, and Clock Generator Control Registers. Updated This Figure through This Figure. Added This Figure.

Chapter 38: Updated Introduction, Functional Description, and Register Overview. Revised This Figure.

Chapter 39: Updated Introduction, JTAG Chain, and CoreSight Functional Description. Revised This Figure, This Figure, This Figure, This Figure, and This Figure.

03/31/2017

 

1.5

 

Chapter 2: Revised the Introduction section including This Figure. Restructured chapter, including revising Table: Power Pins through Table: System Debug Signals and Interfaces.

Chapter 3: Revised Cortex-A53 MPCore Processor Features, Arm v8 Architecture, Power Islands, and Application Processing Unit Reset.

Chapter 4: Revised Real-time Processing Unit Features, RPU CPU Configuration, and Lock-step Operation.

Chapter 5: Added Note to Programming the Mali GPU.

Chapter 6: Revised This Figure and This Figure. Revised Low-Power Operation Mode, including adding Table: Minimum and Typical Configurations for the Low-Power Mode. Revised Full-Power Operation Mode. Added Note to PMU Processor and before Table: Deep-sleep Configuration. Added MBIST and Scan Clear Functionality and Interacting with the PMU sections. Revised Table: I/O Registers.

Chapter 7: Revised This Figure. Updated RTC Controller Unit, RTC Clock Generation, Specifying the RTC Battery, RTC Controller, and Programming Model. Updated Table: RTC Register List.

Chapter 8: Updated chapter title. Revised Functional Safety Overview and Functional Safety Software Test Library. Revised Figure 8-1. Removed Security Features section.

Chapter 9: Revised Introduction and Features. Revised Table: PS SYSMON and PL SYSMON Comparison. Added Table: PS SYSMON Sensor Channels. Updated This Figure.

Chapter 10: Revised This Figure. Updated Table: Top-Level System Address Map, Table: CSU, PMU, TCM, and OCM Address Space, and Table: System-level Register Sets through Table: PS System Register Map (LPD).

Chapter 11: Updated Introduction, Boot Flow, Boot Modes, Golden Image Search, Loopback Mode, and Initialize PCAP Interface. Revised Table: Boot Modes, Table: Boot Image Search Limits, Table: QSPI Command Codes, Table: Boot Header Format, Table: BootROM Error Bits, and Table: BootROM Error Codes. Updated This Figure and This Figure.

Chapter 12: Updated chapter title. Updated Introduction, Secure Processor Block, Crypto Interface Block, Tamper Monitoring and Response, Key Management Summary, and Secure Boot. Added Device and Data Security and Protecting Test Interfaces. Revised This Figure, This Figure, This Figure, This Figure, This Figure, and This Figure. Added Table: Tamper and Control Registers Channels, Table: External Tamper Detect Signal on MIO, Table: Tamper Monitor and Response Bits, Table: Types of Keys, Table: PUF Helper Data, Table: CSU User Commands, Table: PUF Control eFUSEs, Table: Zynq UltraScale+ MPSoC Security eFUSEs, Table: PMU Security Operations, and Table: Public Keys. Added This Figure, This Figure, This Figure, This Figure, This Figure, This Figure, This Figure, This Figure, Figure 12-18, Figure 12-19, and Figure 12-20.

Chapter 13: Revised Introduction. Added System Interrupts, including Table: System Interrupts. Added GIC Interrupt System Architecture, RPU GIC Interrupt Structure, APU GIC Interrupt Controller, IPI Interrupts and Message Buffers, GIC Proxy Interrupts, and CPU Private Peripheral Interrupts. Revised This Figure, This Figure, This Figure, and This Figure. Revised Table: IPI Channel and Message Buffer Default Associations, Table: Interrupt Register Overview, and Table 13-6.

03/31/2017

1.5 (cont’d)

Chapter 14: Reorganized and revised entire chapter, including the changes listed here. Updated chapter title. Updated Introduction, including revising This Figure. Added APU MPCore System Counter and APU Core Private Physical and Virtual Timers. Revised Triple-timer Counters and System Watchdog Timers. Revised This Figure and This Figure. Revised Table: AArch32 Register Overview through Table: Watchdog Timers. Revised Table: TTC Stop Timer through Table: SWDT I/O Control and Configuration Register Sets.

Chapter 15: Revised Full Power Domain, including adding This Figure and This Figure. Revised, including adding Low Power Domain in This Figure and Figure 15-5.

Chapter 16: Revised This Figure. Revised Table 1. Revised AXI and APB Isolation Block.

Chapter 17: Revised This Figure, This Figure, This Figure, Figure 17-18, and Figure 17-21. Revised DDR Memory Controller Features, DDR Subsystem Functional Description, Debugging PS DDR Designs, and DDR Memory Controller Programming Model. Revised Table: DDR Memory Controller Conditions, Table: Example Memory Configurations, Table: DDR Pins, Table: PHY General Status Register 0 (PGSR0) through Table: DDRPHY Registers.

Chapter 18: Revised Introduction, On-chip Memory Functional Description, On-chip Memory Register Overview, and On-chip Memory Programming Model. Revised This Figure and This Figure. Updated Table: OCM Mapping Summary and Table: OCM Register Overview.

Chapter 19: Revised Introduction, DMA Controller Functional Description, DMA Data Flow, DMA Interrupt Accounting, DMA Over Fetch, and DMA Programming Model for FCI. Revised Table: DMA Controller Registers.

Chapter 20: Revised Functional Description, Clocks, Resets, Controller Modes, Message Format, Message Buffering, Interrupts, RX Message Filtering, and CAN0-to-CAN1 Connection. Updated This Figure and This Figure. Revised Table: CAN Reset Effects, Table: CAN Controller Modes of Operation, Table: CAN Message Format, Table: List of CAN Status and Interrupts, and Table: CAN Message Acceptance Mask and Identifier Register Bit Fields.

Chapter 22: Revised This Figure. Updated Glitch Filter, revised Table: I2C Register Overview through Table 22-29.

Chapter 23: Revised Table: SPI MIO Pins, Table: SPI EMIO Signals, and Table: SPI Abort and Reset.

Chapter 24: Revised Controller Features and Quad-SPI Feedback Clock . Added Linear Addressing Mode (Memory Reads).

Chapter 25: Revised Features and AXI Interface.

Chapter 26: Updated System/Host Interfaces, Non-DLL Mode Clocking, DLL Mode, and SD Tap Delay Settings. Revised Table: SD Card Speed Modes(1), Table: eMMC Speed Modes, and Table: Non-DLL Mode Frequencies through Table: eMMC DDR Mode. Revised This Figure.

Chapter 27: Updated Features, SDK and Hardware Design, Functional Description, MIO Pin Configuration, GPIO Channel Architecture, Device Pin Channels, MIO Signals, EMIO Signals, Interrupt Function, System Interfaces, Register Overview, and Programming Model. Revised Table: GPIO Interrupt Trigger Settings, through Table: Wait for Interrupts from all the GPIO Inputs to Exit. Updated This Figure and Figure 27-4.

Chapter 28: Updated Introduction and Multiplexed I/O Programming Model - Example. Revised This Figure. Revised Table: MIO Interfaces and Table: MIO Control Registers.

Chapter 29: Revised This Figure, Data Selection Multiplexer, Predriver, and Voltage Mode Driver, and Table: CMOS-level Clocks. Removed Transmitter Boundary Scan, Boundary Scan Receiver, and SIOU Registers sections.

Chapter 30: Added Important Note in PCIe Domain Interrupts. Revised Important Note in Card to System Flow (EP Memory to Host Memory).

3/31/2017

1.5 (cont’d)

 

Chapter 31: Added Note to USB 2.0/3.0 Host, Device, and USB 2.0 OTG Controller Features.

Chapter 32: Updated Features, SATA Host Controller Interface Description, AXI Master Port Security Features, and AXI Slave Port Security Features. Revised This Figure and This Figure. Updated Table: Program SATA Clock.

Chapter 33: Revised Introduction, Features, DisplayPort DMA, and Register Overview. Updated This Figure and This Figure. Revised Table: DisplayPort Configuration Registers, Table: DisplayPort DMA Registers, and Table: Source Controller Setup and Initialization.

Chapter 34: Revised IEEE Std 1588 Time Stamp Unit, Configure the Controller, Status and Wakeup Interrupts, Transmitting Frames, Receiving Frames, and Gigabit Ethernet Debug Guide. Added note to Gigabit Ethernet Controller using EMIO. Revised Recommended note in Configure the Buffer Descriptors.

Chapter 35: Revised Programmable Logic Introduction, PS-PL Interface Features. Updated Note in AXI Interface Programming. Updated Table: PL Master Registers. Revised This Figure.

Chapter 36: Added High-Speed Transceivers (GTH Quad and GTY Quad) and DisplayPort Video and Audio Interfaces.

Chapter 37: Revised This Figure and This Figure. Updated Clocking Functional Description, LSBUS Clock, and TOPSW Main Clock.

Chapter 39: Updated Features, JTAG and DAP Functional Description, and JTAG Chain Configuration. Added Note to JTAG Error Status Register.

2/02/2017

1.4

Chapter 11: Added an Important note on page 195.

Chapter 20: Removed Step 1F on page a452, and Step 1F and Step 2F on page 471.

Chapter 30: Updated the Important note on page 773.

Chapter 34: Added a Tip on page 976.

Chapter 35: Updated the Note on page 1001. Updated Table: PL Master Registers.

10/25/2016

1.3

Added the dual-core Arm® Cortex™-A53 MPCore™ revisions throughout. Added Chapter 7 and Chapter 8.

Chapter 1: Updated This Figure, Table: Functional Units and Peripherals, and the Register Reference with clarifications.

Chapter 2: Revised the Introduction section including This Figure. Updated the AXI Interfaces section and Table: Processor Communications. Revised the Processor Communications section. Revised the section including adding examples. Added the PS-PL Miscellaneous Signals section. Added comments to Table: System Debug Signals and Interfaces.

Chapter 3: Updated the I/O Coherency section. Updated and moved the ACE Master Interface section. Updated the Individual MPCore Shutdown Mode section. Revised This Figure.

Chapter 4: Added the Interrupt Injection Mechanism section. Update Table: TCM Address Map.

Chapter 6: Updated the chapter including removing Figure 6-1: Power Modes. Revised This Figure and This Figure. Updated the descriptions in the PMU RAM, PMU GPIs and GPOs, and PMU Programmable Interval Timers sections and removed sections of Table: Deep-sleep Configuration. Clarification of some descriptions in the Platform Management Unit Operation section. Updated the Reset Services section. Updated and added the register type to Table: I/O Registers.

Chapter 9: Revised the PS and PL System Monitor Programming Model section including replacing PSSYSMON with AMS_PS_SYSMON and PLSYSMON with AMS_PL_SYSMON.

Chapter 10: Edited the Global Address Map discussion including This Figure. Updated the start addresses for R5_0_ATCM_LSTEP and R5_0_BTCM_LSTEP in Table: CSU, PMU, TCM, and OCM Address Space. Added the PL AXI Interface section. Updated the S_AXI_HPCx_FPD address descriptions in Table: PS System Register Map (LPD).

Chapter 11: Updated This Figure. Added the Tip on page 197. Updated the offset 0x038 description in Table: Boot Header Format.

Chapter 12: Updated the Key Management section including This Figure. Updated Table: Device DNAIdentifiers, This Figure, This Figure, This Figure, and This Figure. Added the Battery-Backed RAM, Programming the eFUSE, and Reading the eFUSE sections.

10/25/2016

1.3 (cont’d)

Chapter 13: Updated the Interrupts Functional Description section including This Figure. Revised the Shared Peripheral Interrupts section. Updated This Figure and added a note on page 275. Added Table: APU with Interrupt Virtualization Block Diagram and Table: Sender-Receiver Interrupt Functions. Updated This Figure. Updated the start and end ID numbers in Table: IPI Interrupt Channel Architecture. Updated and removed registers in the IPI section of Table: IPI Interrupt Channel Architecture and added a note on page 265. Added the Clearing Pending Interrupts from the APU GICv2 section.

Chapter 14: Updated the Introduction. Revised the Physical Counter, System Watchdog Timers, and Triple-timer Counters sections.

Chapter 15: Revised the Introduction, Interconnect Functional Description, and Quality of Service sections. Revised This Figure and Figure 15-6. Removed the Interconnect Submodules and Interconnect Programming Models sections and added them to Chapter 16.

Chapter 16: Updated the Introduction including adding use cases and a terminology section. Revised This Figure. Numerous updates to the System Protection Unit Functional Description section including further information on poisoning a request. Added the AXI Timeout Block and AXI and APB Isolation Block sections from Chapter 15. In the XMPU Programming section replaced XMPUx with DDR_XMPUx, FPD_XMPU with FPD_XMPU_CFG, and OCM_XMPU with OCM_XMPU_CFG. Added the AXI/APB Isolation Block Programming section from Chapter 15.

Chapter 17: Revised the DDR Memory Controller Features. Revised This Figure. Revised Table: DDR Memory Controller Conditions and Table: Example Memory Configurations. Updated This Figure. Added the SDRAM Address Mapping section. Removed the DDRC traffic class and transaction discussions. Updated the Address Collision Handling section. Revised the Restriction on Data Mask when ECC is Enabled, PHY Utility Block, and Data Training sections and updated This Figure. Replaced This Figure and added This Figure, This Figure, This Figure.

Chapter 18: Updated the Introduction section and added a features list. Added This Figure and the 64-bit ECC Support and Low Power Operation sections.

Chapter 19: Updated the Features section.

Chapter 20: Clarified Introduction and updated This Figure. Updated the Interrupts section.

Chapter 21: Updated the Features section.

Chapter 22: Updated the Introduction section. Updated This Figure. Added I2C Master Mode, I2C Slave Mode, and MIO-EMIO Signals sections. Removed individual register descriptions.

Chapter 24: Updated the Introduction. Updated This Figure and This Figure. Revised Table: Generic FIFO Details. Removed the Read/Write Request Details section. Revised Table: Quad-SPI Command List for Dual Quad-SPI Parallel Mode, Table: Quad-SPI Register Summary, and Table: Quad-SPI Controller at 40 MHz Tap Delay Value. Updated This Figure and This Figure. Added the Controller Features, System-level View, Address Map and Device Matching For Linear Address Mode, and Legacy Quad-SPI Operating Restrictions sections. Updated the Using the Quad-SPI Controller section. Added the Dynamic Mode and Baud Rate Change Limitations and the Reference Clock Change Limitations sections. Updated the Quad-SPI Controller Programming and Usage Considerations section.

Chapter 25: Removed the NAND Flash Device Sequence section. Added Change Timing Mode and NVDDR-SDR and ONFI Set Feature tables.

10/25/2016

1.3 (cont’d)

Chapter 26: Added the SD Host Controller Operation section. Updated the bit field descriptions around This Figure. Added the SD Tap Delay Settings section. Revised Table: SD HSD Mode and Table: eMMC HSD Mode. Added Table: SDIO Interface Signals.

Chapter 27: Moved the PS-PL MIO-EMIO Signals and Interfaces section from Chapter 28. Updated This Figure and replaced This Figure. Updated the EMIO Signals section. Updated the Clock and Reset sections. Removed the Interrupts section and the MIO Programming section. Revised the register names in Table: GPIO Interface Signals via MIO Pins.

Chapter 28: Revised the Multiplexed I/O Functional Description sections including the Output Multiplexer descriptions. Moved the Output MultiplexerPS-PL MIO-EMIO Signals and Interfaces section to Chapter 27. Added the Drive Strength section. Updated Note 1 in Table: MIO Interfaces and Table: MIO Control Registers. Updated the register fields in Table 28-4 and Table 28-5.

Chapter 29: Updated This Figure and the PS-GTR Transceiver Interface Features section. Updated This Figure. Updated the Interconnect Matrix section to focus on using the PCW. Updated This Figure and This Figure. Removed Figure 29-5 and the PLL Clock and Reset Distribution section. Added the Spread-Spectrum Clocking Transmitter Support section. Updated This Figure Added the Spread-Spectrum Clocking Receiver section. Removed the PS-GTR Eye Scan section including Figure 29-10, Figure 29-11, and Table 29-5. Added the TX Configurable Driver section. Updated the PS-GTR Transceiver Register Overview and PS-GTR Transceiver Programming Considerations sections.

Chapter 30: Updated This Figure, This Figure, This Figure, This Figure, Table: Clock Description, and Table: Reset Description. Added an Important note on page 752 and another note on page 753. Added the PCIe and AXI Domain Interrupts section. Added a note on page 761. Added the Programmed I/O Transfers section including This Figure and This Figure.

Chapter 31: Added base addresses of the USB controllers on page 815.

Chapter 32: Updated the SATA Host Controller Interface Description. Added an Important note to page 835. Updated the Link Layer section and added This Figure and This Figure. Added the SATA Clocking and Reset section. Added register addresses to Table: SATA Host Bus Adapter Memory Registers through Table: Program SATA Clock. Added PM clock frequency selection rows to Table: PHY Configuration.

Chapter 33: Revised entire sections including the Introduction. After removing the DisplayPort Controller Blocks section, moved This Figure to the DisplayPort Controller System Viewpoint section. Added and revised a significant portion of the DisplayPort Controller Functional Description and DisplayPort Controller Programming Considerations sections. Updated the graphics in the Supported Video Formats section.

Chapter 34: Updated the GEM Features list. Added an Important note on page 942 and a Tip on page 943. Added the Clock Control Register section.

Chapter 35: Updated This Figure. Updated the Recommended note on page 998. Updated the ACP Limitations section. Added the CG devices and revised the bitstream length values for the ZU7EV in Table: PL Master Registers. Added an Important note on page 1026. Updated the register names in Table 35-9.

Chapter 37: Updated This Figure and the paragraph that follows on page 1040. Added the LSBUS Clock section. Clarifying edits to the Full-Power Domain section.

Chapter 38: Updated the Reset System Functional Description section and added This Figure. In Table: Resets, added PS_POR_B and updated SRST_B. Added Table: System Reset Input Pins That Can Reset the PL Configuration.

10/25/2016

1.3 (cont’d)

Chapter 39: Updated the System Test and Debug Features section. Moved the following sections: System Test and Debug and JTAG and DAP Functional Description. Updated Table: POR Boot State and Secure Boot Mode and added Note 1. Updated Table: PJTAG Boot Mode. Revised This Figure. Updated Table: Debug Authentication.

6/01/2016

1.2

Chapter 1: Added the Register Reference section.

Chapter 2: Combined Table: Clock, Reset, and Configuration Pins and Table 2-4.

Chapter 3: Added further descriptions on page 39. Added This Figure and This Figure. Added an important note to page 53.

Chapter 4: Updated the Normal (Split) Operation description. Added the Lock-step Sequence in Cortex-R5 Processors section.

Chapter 5: Added a recommendation on page 94.

Chapter 6: Added the Power Modes section. Updated the PMU System-level View section. Updated the descriptions in Table: PMU General Purpose MIO Pins. Revised descriptions in the PMU Clocking section. Removed PMU local registers from Table: GPI1 Bit Descriptions. Updated descriptions in Table: JTAG Error Register Description. Replaced Table: Deep-sleep Configuration and Table: I/O Registers. Updated register names in the Power Down and Power Up sections. Updated the Isolation Request description.

Chapter 9: Updated the Features descriptions. Revised the steps in the PS and PL System Monitor Programming Model and added the PL SYSMON programming steps.

Chapter 11: Revised SD1/MMC33 and SD1-LS in Table: Boot Modes. Revised the SD0/SD1/MMC section and added SD1-LS support on page 197. Added Table: QSPI Command Codes. Clarifying edits to This Figure and the Initialize PCAP Interface section.

Chapter 12: Clarified the secure processor reset in This Figure.

Chapter 13: Updated XPPU in Table: Interrupt Register Overview.

Chapter 14: Revised the Physical Counter description. Added the CSU_WDT to the System Watchdog Timers discussion.

Chapter 15: Updated the device names in Table: XMPU Register Summary.

Chapter 16: Added further address definition on page 347. Added Note 1 to Table: Peripherals Secured by FPD_XMPU. Added further information after Table: XMPU Configuration Table.

Chapter 17: Added the DDR Memory Types, Densities, and Data Widths section and updated the Traffic Classes section.

Chapter 19: Added This Figure.

Chapter 24: Revised the descriptions and content in Table: 3-Byte Address Support, Table: Quad‐SPI Dual Slave Select 8‐bit Parallel I/O Data Management, and Table: Quad-SPI Register Summary.

Chapter 25: Added a recommendation on page 627..

Chapter 26: Clarified eMMC throughout chapter. Updated eMMC Card Interface section. Updated This Figure. Added Note 1 to Table: SD Commands. Added an important note to page 686. Updated This Figure.

Chapter 28: Updated Table: MIO Control Registers (QSPI pins 1-4, 8-11) and added Note 1 to SD0/1.

Chapter 29: Updated Figure 29-5.

Chapter 30: Updated the Configuration Control (APB Interface) section. Revised the Power Management section discussion on ASPM. Added important notes in the Accessing Bridge Internal Registers section. Added information on Endpoint Compliance. Added a Tip on page 762. Added an important note on page 773.

6/01/2016

1.2 (cont’d)

Chapter 33: Added This Figure to the DisplayPort Controller Blocks section. Added the Supported Video Formats section.

Chapter 34: Added clock restrictions generating a reference clock for GEM on page 938. Added a note on page 946.

Chapter 35: Added SACEFPD_ACLK to Table: Additional Per Port HP I/O Signals.

Chapter 37: Updated the Tip on page 1037 and updated an important note and added a new Tip on page 1038. Updated This Figure, This Figure, and This Figure. Added Table: PLL Integer Feedback Divider Helper Data Values and Table: Clock Configuration Registers. Updated the Programmable Clock Throttle section.

Chapter 39: Updated the JTAG and DAP Functional Description section. Updated the Third-Party Tool Support.

3/07/2016

1.1

Chapter 1: Updated the System Block Diagram section and the LLPP in This Figure.

Chapter 2: Updated This Figure, Table: Power Pins, Table: Clock, Reset, and Configuration Pins, and Table: PS JTAG Interface Pins. Removed Table 2-7: Debug Pins and Associated Signals. Updated Table: Processor Communications. Revised the Interrupts discussion. Revised Table: System Debug Signals and Interfaces.

Chapter 4: Updated the Normal (Split) Operation and TCM Access from a Global Address Space sections.

Chapter 6: Updated This Figure. Revised the Platform Management Unit Functional Description section. Clarified descriptions in the PMU GPIs and GPOs section. Removed Table 6-12: PMU Dedicated I/O. Removed the Use Case for System-level Reset section.

Chapter 9: Updated the Introduction. Updated This Figure and Table: PL SYSMON Sensor Channels. Removed Table 7-4: PS SYSMON Block Auxiliary Channel Registers. Updated Table 9-9.

Chapter 10: Updated the PMU_ROM in Table: CSU, PMU, TCM, and OCM Address Space.

Chapter 11: Revised This Figure, Table: Boot Modes, Table: Boot Header Format, and Table: Image Attributes Offset Definition. Expanded the Boot and Configuration Functional Description section. Added a recommendation to the Boot Modes section. Updated the Initialize PCAP Interface section.

Chapter 12: Added the Tamper Monitoring and Response section. Moved the Secure Stream Switch section to Chapter 11. Updated the Family Key description. Updated the Key Management, RSA Accelerator, and RSA Operations sections. Added the CSU BootROM Error Codes section. Replaced This Figure. Added the Programming SHA-3 Engine section.

Chapter 13: Revised the RPU GIC Interrupt Structure section.

Chapter 15: Revised This Figure. Removed Figure 13-3: Monitor Points in the LPD and updated the APM Points section. Added Quality of Service section.

Chapter 16: Revised This Figure. Added notes on page 349 and page 351. Updated the section. Added the XMPU SINK Register Summary.

Chapter 17: Revised This Figure. Removed the BIST Loopback Mode section. Updated the Data Training section. Updated Figure 17-20 and Figure 17-21.

Chapter 18: Updated the Introduction. Revised Table: OCM Register Overview and This Figure. Removed the Adjust Extra Margin Access Register section.

3/07/2016

1.1 (cont’d)

Chapter 19: Updated the Simple DMA Mode section and Step 4 under Simple Mode Programming.

Chapter 24: Added the Quad-SPI Tap Delay Circuits section.

Chapter 26: Updated Table: SD HSD Mode and Table: eMMC HSD Mode and the Card Detection section.

Chapter 27: Removed the GPIO Bypass Mode section and Figure 27-4.

Chapter 28: Updated the Boot from SD Card section and added the eMMC Mapping section.

Chapter 29: Updated This Figure. Updated the Reference Clock Network section including Figure 29-5.

Chapter 30: Updated the Controller for PCI Express Features list. Updated This Figure. Updated Table: PCIe Reset Signals on MIO.

Chapter 31: Revised the USB 2.0/3.0 Host, Device, and USB 2.0 OTG Controller Features section.

Chapter 32: Updated the SATA Host Controller Interface Description and TrustZone Support sections.

Chapter 33: Added This Figure.

Chapter 34: Updated the Gigabit Ethernet Controller Introduction and Clock Domains sections. Added the External FIFO Interface section. Updated bit 24 in Table: RX Buffer Descriptor Entry. Minor revisions in the IEEE Std 802.3 Pause Frame Reception and PFC Pause Frame Reception sections.

Chapter 35: Revised This Figure, This Figure, This Figure, This Figure. Added important notes on page 1007 and page 1008.

Chapter 36: Updated This Figure and This Figure.

Chapter 37: Updated the System Viewpoint, APU Clock, and DDR Clock sections. Added the PLL Operation section. Added the Low-Power Domain section to Table: AMBA Interconnect Clock Control. Updated the examples in Clocking Programming Considerations. Added the PLL Integer Divide Programming section.

Chapter 38: Updated the Functional Description section and the Programming Model.

Chapter 39: Added features and a flowchart to the Fabric Trigger Macrocell section. Moved the PJTAG Signals, JTAG Toggle Detect, JTAG Disable, JTAG Error Status Register, and JTAG Boot State. Added This Figure.

11/24/2015

1.0

Initial AMD release.