Additional References

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

56.Recommendation for Applications Using Approved Hash Algorithms

57.SHA-3 Standard: Permutation-Based Hash and Extendable-Output Functions

58.Zynq UltraScale MPSoC Cache Coherency

59.System Software Mutexes on Zynq UltraScale

Revision History

The following table shows the revision history for this document.

Date

Version

Revision

9/15/2022

2.3

Chapter 1: Revised This Figure and Table: Device ID Codes and Minimum Production Revisions.

Chapter 2: Revised Table: Power Pins,Table: Clock, Reset, and Configuration Pins, Table: PS-PL AXI Interfaces Summary

Chapter 3: Added note for clarification to System Memory Virtualization Using SMMU Address Translation.

Chapter 4: Added reference to This Figure.

Chapter 6: Revised This Figure and Table: PMU Error Sources and Reset State Masks.

Chapter 7: Revised This Figure

Chapter 8: Revised Introduction.

Chapter 9: Revised Table: PL SYSMON Sensor Channels.

Chapter 10: Revised This Figure, Table: CPU Private Registers, and added content to System-level Control Registers.

Chapter 11: Updated Boot Modes and PCAP Isolation Wall Control. Revised Table: Boot Header Format, Table: BootROM Error Codes, Table: PL Bitstream Length, and Table: Register Access Range and Boot Mode.

Chapter 12: Updated Key Management and Integration and Test Support (BH RSA Option) sections. Revised Table: Zynq UltraScale+ MPSoC Security eFUSEs.

Chapter 13: Revised Table: System Interrupts and Table: IPI Channel and Message Buffer Default Associations.

Chapter 15: Updated IOP Bus Masters and PS Instances. Revised This Figure and Table: QoS Regulators Mapping.

Chapter 16: Updated XMPU Regions, Region Checking Operation, Configuration, and XPPU Self-Protection. Revised Table: System Protection Units and Table: Master IDs List.

Chapter 17: Revised This Figure, Table 17-1, and This Figure. Updated Power and Reset, ECC Programming Model, and Programming Topics.

Chapter 19: Updated Introduction. Added new section Total Transferred Bytes Overflow.

Chapter 23: Revised Table: SPI Interrupt Handler.

Chapter 26: Revised This Figure, Table: SD Clock Frequency Change, and Table: SD Change Bus Speed.

Chapter 28: Revised Table: Non-DLL Mode Frequencies.

Chapter 33: Revised Table: DisplayPort Configuration Registers.

Chapter 34: Revised This Figure.

Chapter 35: Revised This Figure, This Figure, Table: PS-PL Interface Summary, This Figure, This Figure, This Figure, and Table: PS-PL Interrupts Summary.

Chapter 37: Revised Table: LPD Peripheral Clock Control and Table: FPD Peripheral Clock Control.

12/04/2020

2.2

Chapter 1: Revised This Figure, Table: Device ID Codes and Minimum Production Revisions, and Table: System Features Assigned by Software.

Chapter 2: Table: Power Pins and Table: Clock, Reset, and Configuration Pins.

Chapter 4: Revised Table: RPU Pin Configuration and TCM Access from a Global Address Space.

Chapter 6: Revised.

Chapter 11: Revised.

Chapter 12: Revised.

Chapter 13: Revised.

Chapter 14: Revised Event Streams, Generic Timer Programming, Event Control Timer Operation, System Watchdog Timers, Table: MIO – EMIO Signals,

Chapter 15: Revised This Figure, Programming, Table: APM Units, Register Overview, Table: QoS Regulators Mapping

Chapter 16: Revised Table: , added Table: CCI Registers

Chapter 17: Revised section and added Dynamic DDR Configuration section.

Chapter 18: Revised Features.

Chapter 19: Revised Simple DMA Mode, Scatter Gather DMA Mode and Rate Control sections.

Chapter 23: Revised the Clocks section and Table: SPI Set Options.

Chapter 24: Revised Quad-SPI Feedback Clock, Table: Generic FIFO Details, Quad-SPI Tap Delay Values

Chapter 25: Revised This Figure and This Figure.

Chapter 26: Revised Table: SDIO Interface Signals.

Chapter 28: Revised Default Logic Levels section. Added Table: MIO Interfaces.

Chapter 29: Revised Features, Table: TX Configurable Driver Attributes, Receiver Termination

Chapter 30: Revised the Bridge Initialization section.

Chapter 31: Revised USB Controller Features, Register Overview, Table: Groups of Register Map

Chapter 32: Revised Features and This Figure.

Chapter 33: Revised Table: PS-PL Signals for the Live Video Interface, Audio Metadata, DisplayPort DMA, CRC Field, and Table: DPAUX Interface Signals.Chapter 34: SGMII, 1000BASE-SX, or 1000BASE-LX, RX Buffers, IEEE Std 1588 Time Stamp Unit, and Table: Ethernet GMII/MII Interface Signals via EMIO Interface. Added Precision Time Protocol via EMIO and Priority Queuing

Chapter 35: Revised Table: AXI Interfaces and Associated Registers and Table: PS-PL AXI Interfaces.

Chapter 37: Revised Choosing a Programmable Logic Interface and Table: System PLL Clock Control Register Settings.

Chapter 38: Revised Table: Resets and RPU Reset Sequence. Added PL Configuration Reset.

Chapter 39: Revised This Figure, MBIST, LBIST, and Scan Clear (Zeroization), and Table: Scan Clear TRIG and ACK Register Bit Fields

8/21/2019

2.1

 

Chapter 12: Revised Encrypt Only Secure Boot Details section.

Chapter 15: Revised the QoS Regulator section. Updated This Figure.

7/22/2019

2.0

Chapter 1: Revised the JTAG IDCODE section.

Chapter 4: Revised the RPU Pin Configuration section.

Chapter 5: Revised the Programming the GPU. Note updated.

Chapter 6: Revised Full-Power Operation Mode section, Table: Global Registers and added Table 6-14.

Chapter 11: Revised Boot Modes section, PL Bitstream section and added Table: Register Access Range and Boot Mode.

Chapter 12: Revised Secure Lockdown, SHA-3/384, Boot Operation, Encrypt Only Secure Boot Details, and Loading Bitstreams sections.

Chapter 14: Revised APU Core Private Physical and Virtual Timers and Watchdog Enabled on Reset sections.

Chapter 15: Revised Programming and PS Instances sections.

Chapter 17: Revised Table 17-1 and PHY Description section.

Chapter 20: Revised RX/TX Bit Timing Logic section.

Chapter 24: Revised Reference Clock and Quad-SPI Interface Clocks, Quad-SPI Feedback Clock, and Quad-SPI Tap Delay Values sections.

Chapter 26: Revised Tuning Unit, RX Clock Delay Unit, and Receive Clock Tap Delay sections.

Chapter 29: Revised the EyeScan Module section.

Chapter 30: Revised the Features section, added a note in Integrated Block for PCI Express section, and added an Important note in Single CPU Control section.

Chapter 33: Revised Table: PS-PL Signals for the Live Video Interface.

Chapter 34: Added a note under Table: TX Status Errors.

Chapter 35: Revised the LPD-PL Interfaces section.

Chapter 39: Revised the Toggle Detect on PSJTAG, PL TAP Controller, Trace Debug, Security, Components sections and updated Table: PS TAP Controller Status Register and Table: MBIST Control Register Bit Fields.

Appendix A: Arm References updated.

1/17/2019

1.9

Chapter 1: Revised This Figure.

Chapter 2: Revised Table: Clock, Reset, and Configuration Pins.

Chapter 3: Revised System Virtualization and Power Modes sections.

Chapter 4: Revised Tightly Coupled Memory Address Map section.

Chapter 6: Revised This Figure, This Figure, Table: PMU General Purpose MIO pins, MIO Pin Considerations, Table: PMU Error Sources and Reset State Masks, and MIO Signals.

Chapter 7: Revised.

Chapter 8: Entire chapter revised.

Chapter 9: Revised Table: PS SYSMON and PL SYSMON Comparison, Register Sets, and Table: PL SYSMON Unit Register Access Interfaces.

Chapter 11: Revised Table: Boot Modes and Table: Boot Header Format.

Chapter 12: Revised PUF Operations, This Figure, Programming AES-GCM Engine, RSA Accelerator, Security Related eFUSEs, Secure Boot Introduction, Secure Boot Summary, Loading Bitstreams, This Figure, and Secure Boot Image Format. Added Device DNA Identifiers, Initialization Vector Register, Secure Non-Volatile Storage, and Enhanced SPK Revocation. Added note to Table: Zynq UltraScale+ MPSoC Security eFUSEs.

Chapter 13: Revised SPI Interrupt Sensitivity.

Chapter 14: Revised TTC Counter Features, TTC Block Diagram, Table: SWDT I/O Control and Configuration Register Sets, and Table: SWDT Register Overview.

Chapter 15: Revised.

Chapter 16: Revised TBU Instances.

Chapter 17: Table 17-1, Table: Example Memory Configurations table note added, and added a note after the third item in ECC Poisoning Multi-Purpose Register (DDR4 Only).

Chapter 20: Revised.

Chapter 21: Revised.

Chapter 22: Revised Configure Clocks

Chapter 23: Revised Table: SPI EMIO Signals, This Figure, FIFOs, and Clocks, Resets.

Chapter 24: Revised Clocks and Resets, Table: Generic FIFO Details, Table: Generic Quad-SPI Controller: SPI Mode Commands, Table: Generic FIFO Contents for Read Command, Table: Generic FIFO Contents for Quad I/O Read Command, Table: Generic FIFO Contents for Quad Page Program Command, and Table: Quad-SPI Flash Interface Signals.

Chapter 26: Revised Reference Clock, Interface Controller, DLL Clock Mode, Transmit CMD/DAT Delay, Receive Clock Tap Delay, Table: SD DDR Mode, Table: SD Controller Register Overview, Table: SD Clock Frequency Change, Table: SD Card Initialize, and Table: eMMC Card Initialize.

Chapter 27: This Figure updated.

Chapter 28: Default Logic Levels revised.

Chapter 31: Device Programming revised.

Chapter 33: This Figure and This Figure updated.

Chapter 34: Configure the PHY revised.

Chapter 37: Revised This Figure, This Figure, This Figure, and This Figure.

Chapter 38: Revised Table: Resets to System Elements and FPD Reset Sequence.

8/03/2018

1.8

Chapter 19: Revised

Chapter 20: Revised

Chapter 22: Revised

Chapter 23: Revised

Chapter 24: Revised

Chapter 25: Revised

Chapter 26: Revised

Chapter 27: Revised

Chapter 28: Revised

Chapter 29: Revised

Chapter 30: Revised

Chapter 31: Revised

Chapter 32: Revised

Chapter 33: Revised

Chapter 34: Revised

Chapter 35: Revised

Chapter 36: Revised

Chapter 37: Revised

Chapter 38: Revised

12/22/2017

1.7

Revised Debug Features and added MBIST, LBIST, and Scan Clear (Zeroization).

11/01/2017

1.6

Chapter 1: Revised This Figure. Added This Figure and This Figure. Updated Introduction to the UltraScale Architecture. Added Functional Units and Peripherals, Device ID Codes, IP Revisions, System Software, and, Documentation.

Chapter 2Chapter 2: Revised This Figure. Revised Table: Power Pins, Table: Clock, Reset, and Configuration Pins, Table: MIO Pins, Table: Processor Communications, Table: MIO-EMIO Signals and Interfaces, Table: Miscellaneous Signals and Interfaces, Table: Clock Signals, and Table: Timer Signals. Added Table: PS-PL AXI Interfaces Summary and Table 2-14.

Chapter 3: Revised Application Processor Unit Register Overview and This Figure.

Chapter 5: Revised Graphics Processing Unit Introduction, Graphics Processing Unit Level 2 Cache Controller, and Graphics Processing Unit Programming Model.

Chapter 6: Revised Introduction. Updated Table: Minimum and Typical Configurations for the Low-Power Mode and This Figure. Revised This Figure and This Figure.

Chapter 7: Revised Real Time Clock Introduction and Real Time Clock Functional Description. Updated This Figure, This Figure, and This Figure. Added Interfaces and Signals. Revised Table 7-3.

Chapter 9: Revised entire chapter, including changing chapter name.

Chapter 10: Revised This Figure. Updated Table: Top-Level System Address Map. Updated System Address Register Overview. Added Table: PS System Register Map (FPD).

Chapter 11: Updated Boot and Configuration Introduction, Boot Image Format, and Functional Units. Revised Table: Boot Modes. Updated This Figure and This Figure. Added CSU BootROM Error Codes and PL Bitstream.

Chapter 12: Updated Device and Data Security and Secure Boot. Revised This Figure, Figure 12-11, and This Figure.

Chapter 13: Revised Interrupts Introduction, System Interrupts, IPI Interrupts and Message Buffers, CPU Private Peripheral Interrupts, and Programming Examples. Updated This Figure and This Figure. Added This Figure.

Chapter 14: Revised APU Core Private Physical and Virtual Timers and System Watchdog Timers.

Chapter 15: Updated Block Diagram, AXI Performance Monitor, Quality of Service, and Interconnect Register Overview. Revised This Figure. Added ATB Timeout Description and Programming Example – Metric Counter. Updated This Figure and This Figure.

Chapter 16: Revised Introduction, TrustZone, SMMU Protection on CCI Slave Ports, XMPU Protection of Slaves, and XPPU Protection of Slaves. Added XMPU Register Set Overview, XPPU Register Set Overview, Programming Example, and Write-Protected Registers Table. Revised This Figure, This Figure, This Figure, and This Figure. Added This Figure, This Figure, and This Figure.

Chapter 17: Revised This Figure, This Figure, This Figure, and This Figure. Updated DDR Memory Controller Introduction, DDR Subsystem Functional Description, Debugging PS DDR Designs, DDR Memory Controller Register Overview, and DDR Memory Controller Programming Model.

11/01/2017

1.6 (cont’d)

Chapter 18: Revised This Figure and updated On-chip Memory Programming Model.

Chapter 19: Updated DMA Controller Introduction, DMA Controller Functional Description, DMA Data Flow, DMA Programming for Data Transfer, and DMA Programming Model for FCI. Updated This Figure.

Chapter 21: Revised This Figure and This Figure. Added This Figure, This Figure, This Figure, This Figure, This Figure, This Figure, and This Figure. Added MIO – EMIO Signals.

Chapter 22: Revised This Figure and This Figure. Updated I2C Controller Functional Description, I2C Controller Register Overview, and I2C Controller Programming Model.

Chapter 23: Revised This Figure. Updated SPI Controller Introduction and Programming Model.

Chapter 24: Revised This Figure, This Figure, This Figure, and This Figure. Updated Introduction, System Control, Generic Quad-SPI Controller, Legacy Quad-SPI Controller, Register Overview, Programming and Usage Considerations, Generic Quad-SPI Controller Programming, and Legacy Quad-SPI Controller Programming.

Chapter 25: Revised Introduction, Functional Description, and NAND Memory Controller Register Overview. Added Clocks and Resets.

Chapter 26: Updated SD/SDIO/eMMC Controller Introduction, SD/SDIO/eMMC Controller Functional Description, and SD/SDIO/eMMC Controller Programming Model. Revised This Figure and This Figure.

Chapter 27: Updated Functional Description and Programming Model.

Chapter 28: Updated MIO Table at a Glance and Register Overview.

Chapter 29: Renamed chapter. Revised Transceivers Introduction, Functional Description, PS-GTR Transceivers Register Overview, and Configuration Program. Updated This Figure, This Figure, and This Figure.

Chapter 34: Renamed chapter. Revised GEM Ethernet Introduction, Functional Description, and GEM Ethernet Programming Model. Revised This Figure and This Figure through This Figure.

Chapter 35: Renamed chapter. Revised PS-PL AXI Interfaces Introduction, Functional Description, Choosing a Programmable Logic Interface, PS-PL Miscellaneous Signals, Processor Event Signals, and Register Overview. Revised This Figure, This Figure, This Figure, This Figure, This Figure, and This Figure.

Chapter 36: Updated PL Peripherals Introduction, PL System Monitor, PL System Monitor, PL System Monitor, Video Codec Unit, GTH and GTY Transceivers, and Interlaken.

Chapter 37: Renamed chapter. Revised Clocking Introduction and Register Overview. Added System PLL Units, Basic Clock Generators, Special Clock Generators, Programming Examples, PLL Integer Divide Helper Data Table, System PLL Control Registers, and Clock Generator Control Registers. Updated This Figure through This Figure. Added This Figure.

Chapter 38: Updated Reset System Introduction, Reset System Functional Description, and Reset System Register Overview. Revised This Figure.

Chapter 39: Updated System Test and Debug Introduction, JTAG Chain:, and CoreSight Functional Description. Revised This Figure, This Figure, This Figure, This Figure, and This Figure.

03/31/2017

 

1.5

 

Chapter 2: Revised the Signals, Interfaces, and Pins Introduction section including Figure 2-1. Restructured chapter, including revising Table 2-1 through Table 2-12.

Chapter 3: Revised Cortex-A53 MPCore Processor Features, ARM v8 Architecture, Power Islands, and Application Processing Unit Reset.

Chapter 4: Revised Real-Time Processing Unit Features, RPU CPU Configuration, and Lock-Step Operation.

Chapter 5: Added Note to Programming the Mali GPU.

Chapter 6: Revised Figure 6-1 and Figure 6-2. Revised Low-Power Operation Mode, including adding Table 6-1. Revised Full-Power Operation Mode. Added Note to PMU Processor and before Table 6-14. Added MBIST and Scan Clear Functionality and Interacting with the PMU sections. Revised Table 6-17.

Chapter 7: Revised Figure 7-1. Updated RTC Controller Unit, RTC Clock Generation, Specifying the RTC Battery, RTC Controller, and Real Time Clock Programming Sequences. Updated Table 7-3.

Chapter 8: Updated chapter title. Revised Functional Safety Overview and Functional Safety Software Test Library. Revised Figure 8-1. Removed Security Features section.

Chapter 9: Revised PS System Monitor Introduction and PS SYSMON Features. Revised Table 9-1. Added Table 9-2. Updated Figure 9-1.

Chapter 10: Revised Figure 10-1. Updated Table 10-1, Table 10-2, and Table 10-4 through Table 10-8.

Chapter 11: Updated Boot and Configuration Introduction, Boot Flow, Boot Modes, Golden Image Search, Loopback Mode, and Initialize PCAP Interface. Revised Table 11-1, Table 11-2, Table 11-3, Table 11-4, Table 11-8, and Table 11-9. Updated Figure 11-1 and Figure 11-2.

Chapter 12: Updated chapter title. Updated Security Introduction, Secure Processor Block, Crypto Interface Block, Tamper Monitoring and Response, Key Management, and Secure Boot. Added Device and Data Security and Protecting Test Interfaces. Revised Figure 12-1, Figure 12-2, Figure 12-9, Figure 12-10, Figure 12-11, and Figure 12-12. Added Table 12-2, Table 12-3, Table 12-4, Table 12-5, Table 12-6, Table 12-7, Table 12-8, Table 12-13, Table 12-14, and Table 12-15. Added Figure 12-4, Figure 12-5 Figure 12-6, Figure 12-7, Figure 12-14, Figure 12-15, Figure 12-16, Figure 12-17, Figure 12-18, Figure 12-19, and Figure 12-20.

Chapter 13: Revised Interrupts Introduction. Added System Interrupts, including Table 13-1. Added GIC Interrupt System Architecture, RPU GIC Interrupt Structure, APU GIC Interrupt Controller, IPI Processor Comm Interrupts, GIC Proxy Interrupts, and CPU Private Peripheral Interrupts. Revised Figure 13-1, Figure 13-2, Figure 13-4, and Figure 13-5. Revised Table 13-3, Table 13-5, and Table 13-6.

03/31/2017

1.5 (cont’d)

Chapter 14: Reorganized and revised entire chapter, including the changes listed here. Updated chapter title. Updated Timers and Counters Introduction, including revising Figure 14-1. Added APU MPCore System Counter and APU Core Private Physical and Virtual Timers. Revised Triple-timer Counters and System Watchdog Timers. Revised Figure 14-2 and Figure 14-3. Revised Table 14-1 through Table 14-4. Revised Table 14-11 through Table 14-22.

Chapter 15: Revised Full Power Domain, including adding Figure 15-2 and Figure 15-3. Revised, including adding Low Power Domain Figure 15-4 and Figure 15-5.

Chapter 16: Revised Figure 16-1. Revised Table 1. Revised AXI and APB Isolation Block.

Chapter 17: Revised Figure 17-1, Figure 17-2, Figure 17-4, Figure 17-18, and Figure 17-21. Revised DDR Memory Controller Features, DDR Subsystem Functional Description, Debugging PS DDR Designs, and DDR Memory Controller Programming Model. Revised Table 17-1, Table 17-2, Table 17-3, Table 17-5 through Table 17-33.

Chapter 18: Revised On-chip Memory Introduction, On-chip Memory Functional Description, On-chip Memory Register Overview, and On-chip Memory Programming Model. Revised Figure 18-1 and Figure 18-2. Updated Table 18-1 and Table 18-2.

Chapter 19: Revised DMA Controller Introduction, DMA Controller Functional Description, DMA Data Flow, DMA Interrupt Accounting, DMA Over Fetch, and DMA Programming Model for FCI. Revised Table 19-5.

Chapter 20: Revised CAN Controller Functional Description, Clocks, Resets, Controller Modes, Message Format, Message Buffering, Interrupts, RX Message Filtering, and CAN0-to-CAN1 Connection. Updated Figure 20-1, Figure 20-3, and Figure 20-3. Revised Table 20-1, Table 20-2, Table 20-3, Table 20-4, and Table 20-5.

Chapter 22: Revised Figure 22-1. Updated Glitch Filter, Revised Table 22-2 through Table 22-29.

Chapter 23: Revised Table 23-1, Table 23-2, and Table 23-4.

Chapter 24: Revised Generic Quad-SPI Controller Features and Quad-SPI Feedback Clock. Added Linear Addressing Mode (Memory Reads).

Chapter 25: Revised NAND Memory Controller Features and AXI Interface.

Chapter 26: Updated System/Host Interface, Non-DLL Mode Clocking, DLL Mode, and SD Tap Delay Settings. Revised Table 26-1, Table 26-2, and Table 26-3 through Table 26-8. Revised Figure 26-2.

Chapter 27: Updated General Purpose I/O Features, SDK and Hardware Design, General Purpose I/O Functional Description, MIO Pin Configuration, GPIO Channel Architecture, Device Pin Channels, MIO Signals, EMIO Signals, Interrupt Function, System Interfaces, Register Overview, and Programming Model. Revised Table 27-1, through Table 27-11. Updated Figure 27-3 and Figure 27-4.

Chapter 28: Updated Multiplexed I/O Introduction and Multiplexed I/O Programming Model – Example. Revised Figure 28-1. Revised Table 28-1 and Table 28-2.

Chapter 29: Revised Figure 29-5, Data Selection Multiplexer, Predriver, and Voltage Mode Driver, and Table 29-5. Removed Transmitter Boundary Scan, Boundary Scan Receiver, and SIOU Registers sections.

Chapter 30: Added Important Note in PCIe Domain Interrupts. Revised Important Note in Card to System Flow (EP Memory to Host Memory).

3/31/2017

1.5 (cont’d)

 

Chapter 31: Added Note to USB 2.0/3.0 Host, Device, and USB 2.0 OTG Controller Features.

Chapter 32: Updated SATA Host Controller Interface Features, SATA Host Controller Interface Description, AXI Master Port Security Features, and AXI Slave Port Security Features. Revised Figure 32-1 and Figure 32-5. Updated Table 32-4 through.

Chapter 33: Revised DisplayPort Controller Introduction, DisplayPort Controller Features, DisplayPort DMA, and DisplayPort Controller Register Overview. Updated Figure 33-18 and Figure 33-20. Revised Table 33-13, Table 33-14, and Table 33-15.

Chapter 34: Revised IEEE Std 1588 Time Stamp Unit, Configure the Controller, Status and Wakeup Interrupts, Transmitting Frames, Receiving Frames, and Gigabit Ethernet Debug Guide. Added note to Gigabit Ethernet Controller using EMIO. Revised Recommended note in Configure the Buffer Descriptors.

Chapter 35: Revised Programmable Logic Introduction, PS-PL Interfaces Features. Updated Note in AXI Interface Programming. Updated Table 35-8. Revised Figure 35-1.

Chapter 36: Added High-Speed Transceivers (GTH Quad and GTY Quad) and DisplayPort Video and Audio Interface.

Chapter 37: Revised Figure 37-1 and Figure 37-2. Updated Clocking Functional Description, LSBUS Clock, and TOPSW Main Clock.

Chapter 39: Updated System Test and Debug Features, JTAG and DAP Functional Description, and JTAG Chain Configuration. Added Note to JTAG Error Status Register.

2/02/2017

1.4

Chapter 11: Added an Important note on page 195.

Chapter 20: Removed Step 1F on page 452, and Step 1F and Step 2F on page 471.

Chapter 30: Updated the Important note on page 773.

Chapter 34: Added a Tip on page 976.

Chapter 35: Updated the Note on page 1001. Updated Table 35-8.

10/25/2016

1.3

Added the dual-core Arm® Cortex™-A53 MPCore™ revisions throughout. Added Chapter 7, Real Time Clock and Chapter 8, Safety.

Chapter 1: Updated Figure 1-1, Table 1-1, and the Register Reference with clarifications.

Chapter 2: Revised the Signals, Interfaces, and Pins Introduction section including Figure 2-1. Updated the AXI Interfaces section and Table 2-5. Revised the Processor Communications section. Revised the  section including adding examples. Added the PS-PL Miscellaneous Signals section. Added comments to Table 2-12.

Chapter 3: Updated the I/O Coherency section. Updated and moved the ACE Master Interface section. Updated the Individual MPCore Shutdown Mode section. Revised Figure 3-8.

Chapter 4: Added the Interrupt Injection Mechanism section. Update Table 4-5.

Chapter 6: Updated the chapter including removing Figure 6-1: Power Modes. Revised Figure 6-1 and Figure 6-2. Updated the descriptions in the PMU RAM, PMU GPIs and GPOs, and PMU Programmable Interval Timers sections and removed sections of Table 6-14. Clarification of some descriptions in the Platform Management Unit Operation section. Updated the Reset Services section. Updated and added the register type to Table 6-17.

Chapter 9: Revised the PS and PL System Monitor Programming Model section including replacing PSSYSMON with AMS_PS_SYSMON and PLSYSMON with AMS_PL_SYSMON.

Chapter 10: Edited the Global Address Map discussion including Figure 10-1. Updated the start addresses for R5_0_ATCM_LSTEP and R5_0_BTCM_LSTEP in Table 10-2. Added the PL AXI Interface section. Updated the S_AXI_HPCx_FPD address descriptions in Table 10-8.

Chapter 11: Updated Figure 11-1. Added the Tip on page 197. Updated the offset 0x038 description in Table 11-4.

Chapter 12: Updated the Key Management section including Figure 12-3. Updated Table 12-11, Figure 12-5, Figure 12-7, Figure 12-10, and Figure 12-11. Added the Battery-Backed RAM (BBRAM), Programming the eFUSE, and Reading the eFUSE sections.

10/25/2016

1.3 (cont’d)

Chapter 13: Updated the Interrupts Functional Description section including Figure 13-1. Revised the Shared Peripheral Interrupts section. Updated Figure 13-4 and added a note on page 275. Added Table 13-3 and Table 13-4. Updated Figure 13-5. Updated the start and end ID numbers in Table 13-5. Updated and removed registers in the IPI section of Table 13-5 and added a note on page 265. Added the Clearing Pending Interrupts from the APU GICv2 section.

Chapter 14: Updated the Timers and Counters Introduction. Revised the Physical Counter, System Watchdog Timer, and Triple-timer Counter sections.

Chapter 15: Revised the Interconnect Introduction, Interconnect Functional Description and Quality of Service sections. Revised Figure 15-1 and Figure 15-6. Removed the Interconnect Submodules and Interconnect Programming Models sections and added them to Chapter 16.

Chapter 16: Updated the System Protection Unit Introduction including adding use cases and a terminology section. Revised Figure 16-1. Numerous updates to the System Protection Unit Functional Description section including further information on poisoning a request. Added the AXI Timeout Block and AXI and APB Isolation Block sections from Chapter 15. In the XMPU Programming section replaced XMPUx with DDR_XMPUx, FPD_XMPU with FPD_XMPU_CFG, and OCM_XMPU with OCM_XMPU_CFG. Added the AXI/APB Isolation Block Programming section from Chapter 15.

Chapter 17: Revised the DDR Memory Controller Features. Revised Figure 17-1. Revised Table 17-1 and Table 17-2. Updated Figure 17-5. Added the SDRAM Address Mapping section. Removed the DDRC traffic class and transaction discussions. Updated the Address Collision Handling section. Revised the Restriction on Data Mask when ECC is Enabled, PHY Utility Block, and Data Training sections and updated Figure 17-8. Replaced Figure 17-14 and added Figure 17-15, Figure 17-16, Figure 17-17.

Chapter 18: Updated the On-chip Memory Introduction section and added a features list. Added Figure 18-1 and the 64-bit ECC Support and Low Power Operation sections.

Chapter 19: Updated the DMA Controller Features section.

Chapter 20: Clarified CAN Controller Introduction and updated Figure 20-1. Updated the Interrupts section.

Chapter 21: Updated the UART Controller Features section.

Chapter 22: Updated the I2C Introduction section. Updated Figure 22-1. Added I2C Master Mode, I2C Slave Mode, and MIO-EMIO Signals sections. Removed individual register descriptions.

Chapter 24: Updated the Quad-SPI Controller Introduction. Updated Figure 24-1 and Figure 24-2. Revised Table 24-3. Removed the Read/Write Request Details section. Revised Table 24-10, Table 24-11, and Table 24-12. Updated Figure 24-3 and Figure 24-4. Added the Legacy Quad-SPI Controller Features, Legacy Quad-SPI Controller System-level View, Address Map and Device Matching For Linear Address Mode, and Legacy Quad-SPI Operating Restrictions sections. Updated the Using the Quad-SPI Controller section. Added the Dynamic Mode and Baud Rate Change Limitations and the Reference Clock Change Limitations sections. Updated the Quad-SPI Controller Programming and Usage Considerations section.

Chapter 25: Removed the NAND Flash Device Sequence section. Added Change Timing Mode and NVDDR-SDR and ONFI Set Feature tables.

10/25/2016

1.3 (cont’d)

Chapter 26: Added the SD Host Controller Operation section. Updated the bit field descriptions around Figure 26-2. Added the SD Tap Delay Settings section. Revised Table 26-9 and Table 26-10. Added Table 26-11.

Chapter 27: Moved the PS-PL MIO-EMIO Signals and Interfaces section from Chapter 28. Updated Figure 27-1 and replaced Figure 27-3. Updated the EMIO Signals section. Updated the Clock and Reset sections. Removed the Interrupts section and the MIO Programming section. Revised the register names in Table 27-3.

Chapter 28: Revised the Multiplexed I/O Functional Description sections including the Output Multiplexer descriptions. Moved the PS-PL MIO-EMIO Signals and Interfaces section to Chapter 27. Added the Drive Strength section. Updated Note 1 in Table 28-1 and Table 28-2. Updated the register fields in Table 28-4 and Table 28-5.

Chapter 29: Updated Figure 29-1 and the PS-GTR Transceiver Interface Features section. Updated Figure 29-2. Updated the Interconnect Matrix section to focus on using the PCW. Updated Figure 29-3 and Figure 29-4. Removed Figure 29-5 and the PLL Clock and Reset Distribution section. Added the Spread-Spectrum Clocking Transmitter Support section. Updated Figure 29-6 Added the Spread-Spectrum Clocking Receiver section. Removed the PS-GTR Eye Scan section including Figure 29-10, Figure 29-11, and Table 29-5. Added the TX Configurable Driver section. Updated the PS-GTR Transceiver Register Overview and PS-GTR Transceiver Programming Considerations sections.

Chapter 30: Updated Figure 30-1, Figure 30-2, Figure 30-3, Figure 30-4, Table 30-1, and Table 30-2. Added an Important note on page 752 and another note on page page 753. Added the PCIe and AXI Domain Interrupts section. Added a note on page page 761. Added the Programmed I/O Transfers section including Figure 30-10 and Figure 30-11.

Chapter 31: Added base addresses of the USB controllers on page 815.

Chapter 32: Updated the SATA Host Controller Interface Description. Added an Important note to page 835. Updated the Link Layer section and added Figure 32-3 and Figure 32-4. Added the SATA Clocking and Reset section. Added register addresses to Table 32-1 through Table 32-4. Added PM clock frequency selection rows to Table 32-7.

Chapter 33: Revised entire sections including the DisplayPort Controller Introduction. After removing the DisplayPort Controller Blocks section, moved Figure 33-1 to the DisplayPort Controller System Viewpoint section. Added and revised a significant portion of the DisplayPort Controller Functional Description and DisplayPort Controller Programming Considerations sections. Updated the graphics in the Supported Video Formats section.

Chapter 34: Updated the GEM Features list. Added an Important note on page 942 and a Tip on page 943. Added the Clock Control Register section.

Chapter 35: Updated Figure 35-1. Updated the Recommended note on page 998. Updated the ACP Limitations section. Added the CG devices and revised the bitstream length values for the ZU7EV in Table 35-8. Added an Important note on page 1026. Updated the register names in Table 35-9.

Chapter 37: Updated Figure 37-2 and the paragraph that follows on page 1040. Added the LSBUS Clock section. Clarifying edits to the Full-Power Domain section.

Chapter 38: Updated the Reset System Functional Description section and added Figure 38-1. In Table 38-1, added PS_POR_B and updated SRST_B. Added Table 38-4.

10/25/2016

1.3 (cont’d)

Chapter 39: Updated the System Test and Debug Features section. Moved the following sections: System Test and Debug and JTAG and DAP Functional Description. Updated Table 39-1 and added Note 1. Updated Table 39-2. Revised Figure 39-2. Updated Table 39-7.

6/01/2016

1.2

Chapter 1: Added the Register Reference section.

Chapter 2: Combined Table 2-2 and Table 2-4.

Chapter 3: Added further descriptions on page 39. Added Figure 3-3 and Figure 3-4. Added an important note to page 53.

Chapter 4: Updated the Normal (Split) Operation description. Added the Lock-step Sequence in Cortex-R5 Processors section.

Chapter 5: Added a recommendation on page 94.

Chapter 6: Added the Power Modes section. Updated the PMU System-level View section. Updated the descriptions in Table 6-3. Revised descriptions in the PMU Clocking section. Removed PMU local registers from Table 6-6. Updated descriptions in Table 6-13. Replaced Table 6-14 and Table 6-17. Updated register names in the Power Down and Power Up sections. Updated the Isolation Request description.

Chapter 9: Updated the PS SYSMON Features descriptions. Revised the steps in the PS and PL System Monitor Programming Model and added the PL SYSMON programming steps.

Chapter 11: Revised SD1/MMC33 and SD1-LS in Table 11-1. Revised the SD0/SD1/MMC section and added SD1-LS support on page 197. Added Table 11-3. Clarifying edits to Figure 11-2 and the Initialize PCAP Interface section.

Chapter 12: Clarified the secure processor reset in Figure 12-7.

Chapter 13: Updated XPPU in Table 13-5.

Chapter 14: Revised the Physical Counter description. Added the CSU_WDT to the System Watchdog Timer discussion.

Chapter 15: Updated the device names in Table 16-8.

Chapter 16: Added further address definition on page 347. Added Note 1 to Table 16-6. Added further information after Table 16-7.

Chapter 17: Added the DDR Memory Types, Densities, and Data Widths section and updated the Traffic Classes section.

Chapter 19: Added Figure 19-5.

Chapter 24: Revised the descriptions and content in Table 24-8, Table 24-9, and Table 24-11.

Chapter 25: Added a recommendation on page 627.

Chapter 26: Clarified eMMC throughout chapter. Updated eMMC Card Interface section. Updated Figure 26-4. Added Note 1 to Table 26-13. Added an important note to page 686. Updated Figure 26-6.

Chapter 28: Updated Table 28-2 (QSPI pins 1-4, 8-11) and added Note 1 to SD0/1.

Chapter 29: Updated Figure 29-5.

Chapter 30: Updated the Configuration Control (APB Interface) section. Revised the Power Management section discussion on ASPM. Added important notes in the Accessing Bridge Internal Registers section. Added information on Endpoint Compliance. Added a Tip on page 762. Added an important note on page 773.

6/01/2016

1.2 (cont’d)

Chapter 33: Added Figure 33-1 to the DisplayPort Controller Blocks section. Added the Supported Video Formats section.Chapter 34: Added clock restrictions generating a reference clock for GEM on page 938. Added a note on page 946.

Chapter 35: Added SACEFPD_ACLK to Table 35-3.

Chapter 37: Updated the Tip on page 1037 and updated an important note and added a new Tip on page 1038. Updated Figure 37-1, Figure 37-2, and Figure 37-3. Added Table 37-1 and Table 37-2. Updated the Programmable Clock Throttle section.

Chapter 39: Updated the JTAG and DAP Functional Description section. Updated the Third-Party Tool Support.

3/07/2016

1.1

Chapter 1: Updated the Block Diagram section and the LLPP in Figure 1-1.

Chapter 2: Updated Figure 2-1, Table 2-1, Table 2-3, and Table 2-2. Removed Table 2-7: Debug Pins and Associated Signals. Updated Table 2-5. Revised the Interrupts discussion. Revised Table 2-12.

Chapter 4: Updated the Normal (Split) Operation and TCM Access from a Global Address Space sections.

Chapter 6: Updated Figure 6-2. Revised the Platform Management Unit Functional Description section. Clarified descriptions in the PMU GPIs and GPOs section. Removed Table 6-12: PMU Dedicated I/O. Removed the Use Case for System-level Reset section.

Chapter 9: Updated the PS System Monitor Introduction. Updated Figure 9-1 and Table 9-3. Removed Table 7-4: PS SYSMON Block Auxiliary Channel Registers. Updated Table 9-9.

Chapter 10: Updated the PMU_ROM in Table 10-2.

Chapter 11: Revised Figure 11-2, Table 11-1, Table 11-4, and Table 11-5. Expanded the Boot and Configuration Functional Description section. Added a recommendation to the Boot Modes section. Updated the Initialize PCAP Interface section.

Chapter 12: Added the Tamper Monitoring and Response section. Moved the Secure Stream Switch section to Chapter 11. Updated the Family Key description. Updated the Key Management, RSA Accelerator, and RSA Operations sections. Added the CSU BootROM Error Codes section. Replaced Figure 12-11. Added the Programming SHA-3 Engine section.

Chapter 13: Revised the RPU GIC Interrupt Structure section.

Chapter 15: Revised Figure 15-1. Removed Figure 13-3: Monitor Points in the LPD and updated the APM Points section. Added Quality of Service section.

Chapter 16: Revised Figure 16-1. Added notes on page 349 and page 351. Updated the SMMU section. Added the XMPU SINK Register Summary and the XMPU SINK Register Summary.

Chapter 17: Revised Figure 17-1. Removed the BIST Loopback Mode section. Updated the Data Training section. Updated Figure 17-20 and Figure 17-21.

Chapter 18: Updated the On-chip Memory Introduction. Revised Table 18-2 and Figure 18-2. Removed the Adjust Extra Margin Access Register section.

3/07/2016

1.1 (cont’d)

Chapter 19: Updated the Simple DMA Mode section and Step 4 under Simple Mode Programming.

Chapter 24: Added the Quad-SPI Tap Delay Circuits section.

Chapter 26: Updated Table 26-9 and Table 26-10 and the Card Detection section.

Chapter 27: Removed the GPIO Bypass Mode section and Figure 27-4.

Chapter 28: Updated the Boot from SD Card section and added the eMMC Mapping section.

Chapter 29: Updated Figure 29-2. Updated the Reference Clock Network section including Figure 29-5.

Chapter 30: Updated the Controller for PCI Express Features list. Updated Figure 30-5. Updated Table 30-10.

Chapter 31: Revised the USB 2.0/3.0 Host, Device, and USB 2.0 OTG Controller Features section.

Chapter 32: Updated the SATA Host Controller Interface Description and TrustZone Support sections.

Chapter 33: Added Figure 33-5.

Chapter 34: Updated the Gigabit Ethernet Controller Introduction and Clock Domains sections. Added the External FIFO Interface section. Updated bit 24 in Table 34-5. Minor revisions in the IEEE Std 802.3 Pause Frame Reception and PFC Pause Frame Reception sections.

Chapter 35: Revised Figure 35-1, Figure 35-4, Figure 35-5, Figure 35-6. Added important notes on page 1007 and page 1008.

Chapter 36: Updated Figure 36-1 and Figure 36-2.

Chapter 37: Updated the System Viewpoint, APU Clock, and DDR Clock sections. Added the PLL Operation section. Added the Low-Power Domain section to Table 37-4. Updated the examples in Clocking Programming Considerations. Added the PLL Integer Divide Programming section.

Chapter 38: Updated the Reset System Functional Description section and the Reset System Programming Model.

Chapter 39: Added features and a flowchart to the Fabric Trigger Macrocell section. Moved the PJTAG Signals, JTAG Toggle Detect, JTAG Disable, JTAG Error Status Register, and JTAG Boot State. Added Figure 39-6.

11/24/2015

1.0

Initial Xilinx release.