The DDRC can execute transactions out-of-order while ensuring that all transactions appear as if they are executed in the order that they are received. Every transaction that requires a response from the DDRC arrives with a token number which is provided back to the Zynq UltraScale+ MPSoC as part of the response. Because the DDRC queues transactions prior to execution, it is possible that multiple transactions to the same SDRAM address can arrive before the first transaction to that address is issued. To enforce ordering of accesses to the same address, the DDRC uses the following algorithm.
•New read colliding with queued read causes no problems. The two reads can end up being executed out-of-order.
•New write colliding with queued write.
°If a write combine is enabled, the DDRC overwrites the data for the old write with the one from the new write and only performs one write transaction (write combine).
°If the write combine is disabled, the DDRC holds the new write transaction in a temporary buffer, applies flow control to prevent more transactions from arriving, and flushes the internal queue holding the colliding transaction until that transaction is serviced. Once completed, the DDRC accepts the new transaction.
•New read (or write) colliding with queued write (or read) respectively. In this case, the DDRC performs the following sequence.
a.Holds the new transactions in a temporary buffer.
b.Applies flow control back at the AXI port interface to prevent more transactions from arriving.
c.Flushes the internal queue holding the colliding transaction until that transaction is serviced.
d.Accepts the new transaction and removes flow control.
•A new read colliding with both read and write can happen when a read collides with a read-modify-write (RMW) command. In this case, the reads are flushed until the read collision is cleared, then the writes are flushed
•A new write colliding with both read and write can happen when a write collides with a RMW command. In this case, the new write is held in a temporary buffer until the read is completed. Then, it is combined with the queued write (if write combine is enabled).
•In a new RMW colliding with queued write case, the new RMW is stored in a temporary buffer until the queued write is completed.