A master that wants to access the DDR provides memory read and write requests using a system address. The system address is the command address of a transaction as presented on one of the XPI data ports. The address mapper block within the DDR controller converts this system address to a physical address. It maps the system address to the SDRAM rank, bank group (for DDR4), bank, row, and column addresses.
The controller supports the definition of up to two disjoint memory regions mapping to the SDRAM consecutive addresses. The system address region specification is the same for all data ports. An error response is not generated by the controller for addresses falling outside the specified address regions. The same address translation is applied from one base address to the next base address. The base addresses must be specified and they cannot overlap. It is assumed that an outside agent can generate address decode errors if errors happen to occur. An example is shown in This Figure.