Address Map and Device Matching For Linear Address Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

When a single device is used, the address map for direct memory reads starts from 0xC000_0000 and increases to a maximum of 0xCFFF_FFFF (256 MB). The address map for a two-device system depends on the memory device and I/O configuration. In a two-device system, the Quad-SPI devices must be from the same vendor and have the same protocol.

The 8-bit parallel I/O configuration also requires that the devices have the same capacity. The address map for the parallel I/O configuration starts from 0xC000_0000 and increases to the address of the combined memory capacities, up to a maximum of 0xDFFF_FFFF (512 MB).

In the 4-bit stacked I/O configuration, the devices can have different capacities, but must have the same protocol. When two different size devices used a 2048 Mb device on the lower address. In this mode, the Quad-SPI 0 device starts at 0xC000_0000 and increases to a maximum of 0xCFFF_FFFF (256 MB). The Quad-SPI 1 device starts at 0xD000_0000 and increases to a maximum of 0xDFFF_FFFF (another 256 MB). If the first device is smaller than 256 MB, then there will be a memory space hole between the two devices.

This Figure shows a block diagram of a linear address mode.

Figure 24-4:      Legacy Linear Controller Block Diagram

X-Ref Target - Figure 24-4

X17787-linear-address-mode-block.jpg