Address Translation and Protection

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

All high-performance interfaces into the FPD pass through the system memory management unit (SMMU).

SMMU translates the address of the incoming master requests to the physical memory address and performs checks for permissions to access that physical address, based on the information provided in the translation page-tables. Refer to SMMU Architecture for further information.

SMMU in the path of these high-performance PL interfaces provides the following support.

Support for the use of virtual addresses (same address as is used by the software application) in the PL masters.

Protection as SMMU performs access checks for a transaction