Aperture Permission List

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The XPPU aperture register structure enumerates the permission settings on each protected peripheral, message buffer, and the Quad-SPI flash memory. Each APERPERM_{000:400} register entry contains the information listed in Table: Aperture Permissions Register Format.

Table 16-11:      Aperture Permissions Register Format

Field Name

Bitfield

Description

PERMISSION

[19:0]

Master ID profile permission. Each of the 20 [PERMISSION] bits correspond to the MASTER_ID{19:0} registers. The [PERMISSION] field helps to determine if the transaction request of the master characterized by a MASTER_ID register is permitted.

0 = not allowed.

1 = allowed.

A 1 in bit position n (n < m) indicates that the nth entry in the master ID list has permission to access the aperture. This check is further qualified by parity and TrustZone checks.

TRUSTZONE

[27]

1 = Secure or non-secure transactions are allowed.

0 = Only secure transactions are allowed.

PARITY

[31:28]

The hardware checks the parity bits for the [PERMISSION] and [TRUSTZONE] bit fields. Software must generate and load the parity bits before the protection unit uses the register.

Four parity bits are added to protect the (TrustZone and permission) fields, which are equally divided into four protected fields. Parity must be computed by software when writing an entry in the aperture permission list. If the controller detects a parity error, then a status bit is set.

Bit [31] is parity for bit [27] and bits [19:15].

Bit [30] is parity for bits [14:10].

Bit [29] is parity for bits [9:5].

Bit [28] is parity for bits [4:0].

The aperture permission list must be completely initialized by software to 0 before the XPPU can be enabled. The software is also required to compute and write parity. For unprotected apertures, all supported master match bits in the permission RAM should be set to 1.