Arm v8 Architecture

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The Arm v8-A is the next generation 64-bit Arm architecture. Arm v8 is backward compatible to Arm v7 (i.e., a 32-bit Arm v7 binary will run on an Arm v8 processor). Although the Arm v8 is backward compatible with the Arm v7 architecture, the Cortex-A53 MPCore is not necessarily backward compatible with Cortex-A9 architecture. This is because some of the Cortex-A9 sub-system functions (e.g., Cortex-A9 L2 control registers) were implementation specific and not part of the Arm v7 architecture.

Arm v8 supports two architecture states.

64-bit execution state (AArch64)

32-bit execution state (AArch32)

AArch32 is compatible with Arm v7; however, it is enhanced to support some features included in AArch64 execution state (for example, load-acquire and store-release). Both execution states support advanced single-instruction multiple-data (SIMD) and floating-point extension for integer and floating-point. Also, both states support cryptography extension for the advanced encryption standard (AES) encryption/decryption, SHA1/256, and RSA/ECC.

This Figure shows the block diagram of the APU.

Figure 3-1:      APU Block Diagram

X-Ref Target - Figure 3-1

X15286-apu-block.jpg

The Arm v8 exception model defines exception levels EL0–EL3, where:

EL0 has the lowest software execution privilege. Execution at EL0 is called unprivileged execution.

Increased exception levels, from 1 to 3, indicate an increased software execution privilege.

EL1 provides support for basic non-secure state.

EL2 provides support for processor virtualization.

EL3 provides support for a secure state.

The APU MPCore processor implements all the exception levels (EL0–EL3) and supports both execution states (AArch64 and AArch32) at each exception level.

When a Cortex-A53 MPCore processor is brought up in 32-bit mode using the APU_CONFIG0 [VINITHI] parameter register, its exception table cannot be relocated at run time. The V[13] bit of the system control register defines the base address of the exception vector.

See the Zynq UltraScale+ MPSoC Software Developer’s Guide (UG1137) [Ref 3] for more information.

This Figure shows a top-level functional diagram of the Cortex-A53 MPCore processor.

Figure 3-2:      APU Block Diagram

X-Ref Target - Figure 3-2

X15287-apu-core-block.jpg