Asserting PWRCTL.en_dfi_dram_clk_disable to Disable the Clocks to DRAM

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Figure 17-13:      Asserting the PWRCTL.en_dfi_dram_clk_disable bit to
Disable the Clocks to DRAM Flowchart

X-Ref Target - Figure 17-13

X15359-dram-disable-flowchart.jpg