Basic Clock Generators

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The basic clock generator is shown in This Figure. The architecture is used for all system elements except the special clock generators for the APU MPCore (This Figure) and the DDR memory controller (This Figure). Variations of the basic clock generator include the number of divider units, the three specific clock sources provided to the clock generator, and the number of clock active controls.

The system PLL clock source is selected using the CRx_APB.xPLL_CTRL [SRCSEL] bit field. The PLL is in bypass or active mode. The selected PLL output goes to a 6-bit clock divider in its native power domain and a 6-bit divider in the other PS power domain.

The CSU BootROM (CBR) and PMU pre-boot ROM code modifies several clock control registers, including divisor values and clock enables. The modifications are described in the System PLL Control Registers and Clock Generator Control Registers sections.

 

IMPORTANT:   All clock generator input multiplexers in This Figure have a default input clock selection of 0. The selected source clock is listed in the register overview tables. Before downloading the first stage boot loader (FSBL), all PLLs except for IOPLL and DPLL are held in reset. The system PLLs are programmed by the FSBL and system software for the application.

Note:   The clock multiplexers within the clock subsystem (system PLLs, basic, and special clock generators) include de-glitching logic to enable changes while the system is operating. However, clock multiplexers out in the system (e.g., I/O controllers) do not generally include this logic. In these cases, clocks might need to be stopped before switching, or the controller needs to be held in reset while switching. Refer to individual cases.

Figure 37-4:      Basic LPD and FPD Clock Generator Block Diagram

X-Ref Target - Figure 37-4

X19872-lpd-fpd-clock-generator-block-diagram.jpg

There are many basic clock generators. Their control registers are listed in the Clock Generator Control Registers section.

Interconnect

RPU MPCore

LPD and FPD DMA units

LPD, FPD, Trace, and Timestamp Debug

PS SYSMON unit

PL

DisplayPort Video, Audio, STC, DMA

GPU

PCIe

SATA

IOP Peripherals (GEM, USB, UART, SPI, Quad-SPI, NAND, SDIO, CAN, I2C)

Several of these clock generators are described in more detail.