Baud Rate Generator

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The baud rate generator furnishes the bit period clock, or baud rate clock, for both the receiver and the transmitter. The baud rate clock is implemented by distributing the base clock UART_REF_CLK and a single cycle clock enable to achieve the effect of clocking at the appropriate frequency division. The effective logic for the baud rate generation is shown in This Figure.

Figure 21-2:      UART Board Rate Generator

X-Ref Target - Figure 21-2

X19864-board-rate-generator.jpg

The baud rate generator can use either the master clock signal, UART_REF_CLK, or the master clock divided by eight, UART_REF_CLK/8. The clock signal used is selected according to the value of the CLKS bit in the Mode register (uart.mode). The resulting selected clock is termed sel_clk in the following description.

The sel_clk clock is divided down to generate three other clocks: baud_sample, baud_tx_rate, and baud_rx_rate. The baud_tx_rate is the target baud rate used for transmitting data. The baud_rx_rate is nominally at the same rate, but gets resynchronized to the incoming received data. The baud_sample runs at a multiple ([BDIV] + 1) of baud_rx_rate and baud_tx_rate and is used to over-sample the received data.

The sel_clk clock frequency is divided by the CD field value in the Baud Rate Generator register to generate the baud_sample clock enable. This register can be programmed with a value between 1 and 65535.

The baud_sample clock is divided by [BDIV] plus 1. BDIV is a programmable field in the Baud Rate Divider register and can be programmed with a value between 4 and 255. It has a reset value of 15, inferring a default ratio of 16 baud_sample clocks per baud_tx_clock / baud_rx_rate.

The frequency of the baud_sample clock enable is shown in This Equation.

Equation 21-1      ug1085_c21_UART00131.jpg

The frequency of the baud_rx_rate and baud_tx_rate clock enables is show in Equation This Equation.

Equation 21-2      ug1085_c21_UART00133.jpg

 

 

IMPORTANT:   It is essential to disable the transmitter and receiver before writing to the Baud Rate Generator register (uart.Baud_rate_gen), or the baud rate divider register (uart.Baud_rate_divider). A soft reset must be issued to both the transmitter and receiver before they are re-enabled.

Some examples of the relationship between the UART_REF_CLK clock, baud rate, clock divisors (CD and BDIV), and the rate of error are shown in Table: UART Parameter Value Examples. The highlighted entry shows the default reset values for CD and BDIV. For these examples, a system clock rate of UART_REF_CLK = 50 MHz and UART_REF_CLK/8 = 6.25 MHz is assumed. The frequency of the UART reference clock can be changed to get a more accurate Baud rate frequency, refer to PS Clock Subsystem for details to program the UART_REF_CLK.

Table 21-1:      UART Parameter Value Examples

Clock

Baud Rate

Calculated CD

Actual CD

BDIV

Actual Baud Rate

Error (BPS)

% Error

UART_REF_CLK

600

10416.667

10417

7

599.980

0.020

-0.003

UART_REF_CLK /8

9,600

81.380

81

7

9,645.061

45.061

0.469

UART_REF_CLK

9,600

651.041

651

7

9,600.614

0.614

0.006

UART_REF_CLK

28,800

347.222

347

4

28,818.44

18.44

0.064

UART_REF_CLK

115,200

62.004

62

6

115,207.37

7.373

0.0064

UART_REF_CLK

230,400

31.002

31

6

230,414.75

14.75

0.006

UART_REF_CLK

460,800

27.127

9

11

462,962.96

2,162.96

0.469

UART_REF_CLK

921,600

9.042

9

5

925,925.92

4,325.93

0.469