The dual-port block buffer (read/write on both ports) stores block data during SD transfers. The block buffer size implemented in the design is 4KB. The block buffer uses a circular buffer architecture. One side of the block buffer is interfaced with the DMA controller and operates at the host clock rate while the other side of the block buffer interfaces with the SD control logic and operates at the SD clock rate. During a write transaction (data transferred from the Arm APU/RPU to the SD 3.0/SDIO 3.0 card), the data is fetched from the system memory and is stored in the block buffer. When a block of data is available, the SD control logic transfers it onto the SD interface. The DMA controller continues to fetch additional blocks of data when the block buffer has space. During a read transaction (data transferred from an SD 3.0/SDIO 3.0 card to the APU/RPU), the data from the SD 3.0/SDIO 3.0 card is written into the block buffer, and at the end when the CRC of the block is valid, the data is committed. When a block of data is available, the DMA controller transfers this data to the system memory. The SD control logic meanwhile receives the next block of data, provided that there is space in the block buffer. If the controller cannot accept any data from an SD 3.0/SDIO 3.0/eMMC 4.51 card, then it will issue a read wait (if the card supports a read wait mechanism) to stop the data transfer from the card or by stopping the clock.
Note: When the block buffer size is twice the block size, the block buffer behaves as a ping-pong buffer.