Block Diagram and Features

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The entire system-level view with both the PL and PS shown This Figure. The PS-PL AXI interfaces are shown in the Programmable Logic (PL), upper right corner.

Figure 35-1:      PS-PL Interfaces

X-Ref Target - Figure 35-1

X2102700243.jpg

The main features of the PS-PL interfaces are summarized in this section.

AXI interfaces provide the following:

°High-performance AXI4 interface with FIFO support in the PS.

-Selectable native PL data bus width support (32/64/128).

-Independent read and write clocks.

-Three interfaces support I/O coherency through the cache-coherent interconnect (CCI).

°System Memory Management Unit (SMMU) for PS bound transactions (virtual to physical address translation).

°Dedicated low-latency path between the low-power domain (LPD) and PL.

°Accelerator coherency port (ACP) interface for I/O coherency and allocation into the APU’s L2 cache.

°AXI coherency extensions (ACE) interface for full coherency. Usable as ACE-Lite
for I/O coherency.

32 bits for general-purpose input and 32 bits for output from the platform management unit (PMU) for communication with the PL.

16 shared interrupts and four inter-processor interrupts.

Dedicated interfaces from the gigabit Ethernet controller (GEM) and the DisplayPort protocol.

Other PS-PL interfaces, such as extended MIO and PL clocks.